SI3460-E03-GM Silicon Laboratories Inc, SI3460-E03-GM Datasheet - Page 14

• Manufacturer Part Number: SI3460-E03-GM
• Description: IC POWER MANAGEMENT CTLR 11VQFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3460-E03-GM

• Package / Case: 11-VQFN
• Applications: Power Sourcing Equipment (PSE)
• Current - Supply: 500mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Product: PoE / LAN Solutions
• Supply Voltage (max): 16 V
• Supply Voltage (min): 11 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 11
• Mounting: Surface Mount
• Package Type: QFN EP
• Case Length: 3mm
• Case Height: 0.83mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si3460
5. Design Considerations
5.1. Isolation
The Si3460-EVB's PSE output power at V
output power requires that the input be isolated from earth ground. Typically, an ac to dc power supply or "wall
wart" is used to provide the 12 V power so the output of this supply is isolated from earth ground.
5.2. External Component Selection
Detailed notes on external component selection are provided in the Si3460-EVB User's Guide schematics and
BOM. In general, these recommendations must be followed closely to ensure output power stability and ripple
(power stage components), surge protection (surge protection diode), and overall IEEE 802.3 compliance.
5.3. Input DC Supply
The input power supply should be rated for at least 25% higher power level than the output power level chosen.
This is primarily to account for the 75 to 80% nominal efficiency performance of the Si3460-EVB reference design.
For example, to support a Class 0 PSE, for example, the input supply should be capable of supplying 19.25 W
(15.4 W x 1.25 = 19.25 W).
5.4. STATUS and RESET Interface
To reference the RESET and STATUS pins to system ground, the level shifting method shown in Figure 3 can be
used. Refer to the schematic in the Si3460-EVB document.
14
Figure 3. STATUS and RESET Pin Interface when Referenced to System Ground
(66.5 k
(40.2 k
+8.7V
+12V
R8
R7
System Gnd


)
)
OUT
RST CONTROL
U1
is not isolated from the input power source (V
Regulator
TLV431
Shunt
806
(1 k
R22
Rev. 1.1


)
1 uF/
6.3 V
RST
STATUS
VDD
Si3460
Output
Status
(332
R*3.3/2.7
405
R40


)
IN
). Isolation of PSE