IR3086AMTRPBF International Rectifier, IR3086AMTRPBF Datasheet - Page 29

• Manufacturer Part Number: IR3086AMTRPBF
• Description: IC CTLR XPHASE 28-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase™r

Specifications of IR3086AMTRPBF

• Package / Case: 20-MLPQ
• Mounting Type: Surface Mount
• Current - Supply: 10mA
• Voltage - Supply: 8.4 V ~ 14 V
• Operating Temperature: 0°C ~ 125°C
• Applications: Processor
• Package: 20-Lead MLPQ
• Circuit: X-Phase Phase IC
• Iout (a): 2.5A Gate Driver
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
• Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and
• Connect PGND to LGND pins of each phase IC to the ground tab, which is tied to LGND and PGND planes
• In order to reduce the noise coupled to SCOMP pin of phase IC, use a dedicated wire to connect the capacitor
• Place current sense resistors and capacitors (R
• Place the decoupling capacitors C
•
•
•
power ground plane (PGND).
respectively through vias.
C
resistor R
connection for the inductor current sense wires, but separate the two wires by ground polygon. The wire from
the inductor terminal to RCS- should not cross over the fast transition nodes, i.e. switching nodes, gate drive
outputs and bootstrap nodes.
respectively.
Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of
the gate drive paths.
Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Use
combination of different packages of ceramic capacitors.
There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output
capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load.
Route the switching power paths using wide and short traces or polygons; use multiple vias for connections
between layers.
SCOMP
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directly to LGND pin. However, connect PWM ramp capacitor C
PHASE2
PLANE
PLANE
PLANE
PLANE
LGND
LGND
PGND
PGND
To PGND
To PGND
To LGND
To LGND
Plane
Plane
Plane
Plane
or R
PHASE3,
To VIN
To VIN
C
C
C
C
VCC
VCC
VCCL
VCCL
decoupling capacitor C
To LGND
To LGND
Plane
Plane
VCC
PWMRMP
PWMRMP
and C
SCOMP
SCOMP
EAIN
EAIN
LGND
LGND
VCC
VCC
To Bottom
To Bottom
VCCL
MOSFET
MOSFET
CS+
as close as possible to VCC and VCCL pins of the phase IC
To Signal Bus
To Signal Bus
VCC
, R
MOSFET
MOSFET
To Top
To Top
CS-
to LGND plane through vias.
, C
Switching
Switching
CS+
Node
Node
To
To
To LGND
To LGND
, and C
CSIN-
CSIN-
Plane
Plane
BIASIN
BIASIN
DACIN
DACIN
PHSFLT
PHSFLT
CSIN+
CSIN+
PWMRMP
CS-
) close to phase IC. Use Kelvin
To Inductor
To Inductor
Ground
Ground
Polygon
Polygon
, phase delay programming
To Gate
To Gate
Voltage
Voltage
Drive
Drive
Ground
Ground
Polygon
Polygon
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