IR3500AMTRPBF International Rectifier, IR3500AMTRPBF Datasheet - Page 21

• Manufacturer Part Number: IR3500AMTRPBF
• Description: IC CTRL XPHASE3 VR11.0 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3500AMTRPBF

• Applications: Processor
• Current - Supply: 6.5mA
• Voltage - Supply: 4.75 V ~ 7.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-MLPQ
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IR3500AMTRPBFTR

Figure 11 depicts start-up sequence of converter with VR 11 VID with boot voltage, which is selected by VIDSEL pin
based on Table 1. If there is no fault, the SS/DEL pin will start charging when the enable crosses the threshold. The
error amplifier output EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the
converter’s output voltage to match the SS/DEL voltage less the 1.4V offset until the converter output reaches the
1.1V boot voltage. The SS/DEL voltage continues to increase until it rises above the 3.0V threshold of VID delay
comparator. The VID set inputs are then activated and VDAC pin transitions to the level determined by the VID
inputs. The SS/DEL voltage continues to increase until it rises above 3.92V and allows the PGOOD signal to be
asserted. SS/DEL finally settles at 4.0V, indicating the end of the soft start.
Figure 12 shows start-up sequence of converter VR 11 VID without boot voltage or AMD Opteron, AMD 6-bit VID
which is selected by VIDSEL pin based on Table 1. If there is no fault, the SS/DEL pin will start charging. The error
amplifier output EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the
converter’s output voltage to match the SS/DEL voltage less the 1.4V offset until the converter output reaches the
level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above 3.92V and allows
the PGOOD signal to be asserted. SS/DEL finally settles at 4.0V, indicating the end of the soft start.
VCCL under voltage lock-out, VID fault modes, over current, as well as a low signal on the ENABLE input
immediately sets the fault latch, which causes the EAOUT pin to drive low turning off the phase IC drivers. The
PGOOD pin also drives low, and SS/DEL begin to discharge until the voltage reaches 0.2V. If the fault has cleared
the fault latch will be reset by the discharge comparator allowing a normal soft start to occur.
Other fault conditions, such as over voltage, open sense lines, open loop monitor, and open daisy chain, set
different fault latches, which start discharging SS/DEL, pull down EAOUT voltage and drive PGOOD low. However,
the latches can only be reset by cycling VCCL power.
ENABLE
VDAC
VRRDY
(12V)
VCC
SS/DEL
EAOUT
VOUT
1.1V
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3.92V
4.0V
1.4V
3V
START DELAY (TD1)
Figure 11 - Start-up sequence of converter with boot voltage
SOFT START
TIME (TD2)
VID SAMPLE
TIME (TD3)
VID
TD4
VRRDY DELAY
TIME (TD4+TD5)
TD5
July 28, 2009
NORMAL OPERATION
IR3500A