STM6503VEAADG6F STMicroelectronics, STM6503VEAADG6F Datasheet - Page 5

• Manufacturer Part Number: STM6503VEAADG6F
• Description: IC DUAL SMART RESET 8TDFN
• Manufacturer: STMicroelectronics
• Series: Smart Reset™r
• Type: Smart Resetr

Specifications of STM6503VEAADG6F

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 1.575V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Current - Supply: 4µA
• Voltage - Supply: 1 V ~ 5.5 V
• Applications: Smart Reset
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Switches: Dual
• Supply Current: 4 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10053-2

STM6502, STM6503, STM6504, STM6505
1
1.1
Description
STM6502 has two combined Smart Reset inputs (SR0 and SR1) with delayed Smart Reset
setup time (t
STM6503 is similar to STM6502, has two combined delayed Smart Reset inputs (SR0, SR1)
and three user-selectable delayed Smart Reset setup time (t
s through a three-state TSR input pin: when connected to ground, t
open, t
STM6504 has two independent Smart Reset inputs. SR0 provides the delayed Smart Reset
setup time (t
input pin: when connected to ground, t
connected to V
is edge-triggered with a special debounce time (t
edge after a valid reset period.
STM6505 has two combined delayed Smart Reset inputs (SR0, SR1) and provides an
adjustable reset delay setup time via an external capacitor connected to the SRC pin.
The RST output depends also on the V
independent low battery detect (BLD) output controlled by the secondary external input
voltage V
detect output pin (BLD). V
be used to set the actual battery voltage threshold. V
(16 mV max.). V
V
Smart Reset devices
The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent
short reset push-button closures do not cause system resets. This is done by implementing
extended Smart Reset input delay (t
delay are met, the device generates an output reset pulse with user-programmable timeout
period (t
The Smart Reset inputs can be also connected to the applications interrupt to allow the
control of both the interrupt pin and the hard reset functions. If the push-buttons are closed
for a short time, the processor is only interrupted. If the system still does not respond
properly, holding the push-buttons for the extended setup time (t
the processor through the reset outputs. The Smart Reset feature helps significantly
increase system stability.
The STM65xx family of Smart Reset devices consists of low current microprocessor reset
circuits targeted at applications such as MP3 players, navigation, smartphones or mobile
phones; generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset inputs
(SR). The delayed Smart Reset setup time (t
adjustable by an external capacitor on the SRC pin or selectable by three-state logic. The
delayed setup period ignores switch closures shorter than t
resets.
CC
pin; V
SRC
REC
BAT
CC
= 6 s; when connected to V
).
SRC
. V
SRC
must be ≥ 1.575 V for proper operation of the V
CC
BAT
) function with three user-selectable t
) programmed by an external capacitor on the SRC pin.
BAT
, t
is monitored for low voltage and provides an indication on the battery low
SRC
is voltage monitoring input only, the device is powered only from the
= 10 s (all the times are minimum). SRE provides instant reset. SRE
BAT
threshold is 1.25 V, fixed, and an external resistor divider is to
Doc ID 16101 Rev 6
SRC
SRC
CC
CC
). Once the valid Smart Reset input levels and setup
, t
monitoring threshold. STM6505 also provides
= 2 s; when left open, t
SRC
SRC
= 10 s (all the times are minimum).
) options of 2 s, 6 s and 10 s (all min.) are
DEBOUNCE
SRC
BAT
threshold hysteresis is 8 mV typ.
options through a three-state TSR
SRC
= 240 ms min.) at the falling
SRC
BAT
, thus preventing unwanted
SRC
) options of 2 s, 6 s and 10
comparator.
SRC
SRC
) causes hard reset of
= 6 s; when
= 2 s; when left
Description
5/29