TDA16888 Infineon Technologies, TDA16888 Datasheet - Page 12

• Manufacturer Part Number: TDA16888
• Description: IC PFC CTRLR AVERAGE CURR 20DIP
• Manufacturer: Infineon Technologies

Specifications of TDA16888

• Mode: Average Current
• Frequency - Switching: 200kHz
• Current - Startup: 50µA
• Voltage - Supply: 0 V ~ 17.5 V
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Switching Frequency: 200 KHz
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000011721; TDA16888X; TDA16888XK

TDA 16888
3
Functional Block Description
Gate Drive
Both PFC and PWM section use fast totem pole gate drives at pin 8 (PFC OUT) and
pin 10 (PWM OUT) respectively, which are designed to avoid cross conduction currents
and which are equipped with Zener diodes (Z1, Z2) in order to improve the control of the
attached power transistors as well as to protect them against undesirable gate
overvoltages. At voltages below the undervoltage lockout threshold these gate drives are
active low. In order to keep the switching losses of the involved power diodes low and to
minimize electromagnetic emissions, both gate drives are optimized for soft switching
operation. This is achieved by a novel slope control of the rising edge at each driver’s
output (see Figure 13).
Oscillator
The TDA 16888’s clock signals as well as the PFC voltage ramp are provided by the
internal oscillator. The oscillator’s frequency is set by an external resistor connected to
pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is
integrated to guarantee a low current consumption and a high resistance against
electromagnetic interferences. In order to ensure superior precision of the clock
frequency, the clock signal CLK OSC is derived from the minima and maxima of a
triangular instead of a saw-tooth signal (see Figure 18). Furthermore, to provide a clock
reference CLK OUT with exactly 50% duty cycle, the frequency of the oscillator’s clock
signal CLK OSC is halved by a D-latch before being fed into the PFC and PWM section
respectively.
V
The ramp signal of the PFC section
is composed of a slowly falling and a
PFC RMP
steeply rising edge, the latter of which is triggered by the rising edge of the clock
reference CLK OUT. This ramp has been reversed in contrast to the common practice,
in order to simultaneously allow for current measurement at pin 5 (GND S) and for
external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC). The
slope of the falling edge, which in conjunction with the output of OP2 controls the pulse-
V
width-modulation of the PFC output signal
, is derived from the current set by the
PFC OUT
external resistor at pin 16 (ROSC). In this way a constant amplitude of the ramp signal
(ca. 4.5 V) is ensured. In contrast, the slope of the rising edge, which marks the minimum
blanking interval and therefore limits the maximum duty cycle
t
of the PFC output
on,max
signal, is determined by an internal current source.
In contrast to the PFC section the ramp signal of the PWM section is trailing edge
triggered with respect to the internal clock reference CLK OUT to avoid undesirable
electromagnetic interference of both sections. Moreover, the maximum duty cycle of the
PWM is limited by the rising edge of the clock reference CLK OUT to 50% to prevent
transformer saturation.
Version 2.0
12
28 Feb 2000