ICE1PCS02 Infineon Technologies, ICE1PCS02 Datasheet - Page 9
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ICE1PCS02
Manufacturer Part Number
ICE1PCS02
Description
IC PFC CONTROLLER CCM 8DIP
Manufacturer
Infineon Technologies
Datasheet
1.ICE1PCS02.pdf
(18 pages)
Specifications of ICE1PCS02
Mode
Continuous Conduction (CCM)
Frequency - Switching
65kHz
Current - Startup
100µA
Voltage - Supply
10.2 V ~ 21 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Through Hole
Package / Case
8-DIP
Switching Frequency
70 KHz
Maximum Operating Temperature
+ 150 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ICE1PCS02X
ICE1PCS02XK
SP000056162
ICE1PCS02XK
SP000056162
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Manufacturer
Quantity
Price
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Manufacturer:
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Quantity:
20 000
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Part Number:
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Manufacturer:
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Part Number:
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Manufacturer:
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Quantity:
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3.4.2
The IC is designed not to support any output power
that corresponds to a voltage lower than -0.73V at the
ISENSE pin. A further increase in the inductor current,
which results in a lower ISENSE voltage, will activate
the Soft Over Current Control (SOC). This is a soft
control as it does not directly switch off the gate drive
like the PCL. It acts on the nonlinear gain block to result
in a reduced PWM duty cycle.
3.4.3
The IC provides a cycle by cycle peak current limitation
(PCL). It is active when the voltage at pin 3 (ISENSE)
reaches -1.08V. This voltage is amplified by OP1 by a
factor of -1.43 and connected to comparator C2 with a
reference voltage of 1.5V as shown in Figure 8. A
deglitcher with 300ns after the comparator improves
noise immunity to the activation of this protection.
Figure 8
3.4.4
Whenever VSENSE voltage falls below 0.8V, or
equivalently V
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage V
normal operation. In this case, most of the blocks within
the IC will be shutdown. It is implemented using
comparator C3 with a threshold of 0.8V as shown in the
IC block diagram in Figure 2.
3.4.5
Whenever V
over-voltage protection OVP is active as shown in
Figure 6. This is implemented by sensing the voltage at
pin VSENSE with respect to a reference voltage of
5.25V. A VSENSE voltage higher than 5.25V will
immediately reduce the output duty cycle, bypassing
the normal voltage loop control. This results in a lower
input power to reduce the output voltage V
Version 1.2
Full-wave
Rectifier
I
R1
INDUCTOR
ISENSE
R2
Soft Over Current Control (SOC)
Peak Current Limit (PCL)
Open Loop Protection (OLP)
Over-Voltage Protection (OVP)
Peak Current Limit (PCL)
OUT
OUT
ICE1PCS02/G
exceeds the rated value by 5%, the
Current Limit
falls below 16% of its rated value, it
1.43x
1.5V
OP1
C2
Deglitcher
300ns
OUT
.
Turn Off
Driver
IN
for
9
3.5
ICE1PCS02/G has an internally fixed switching
frequency as opposed to the ICE1PCS01/G which can
be externally set. This frequency is trimmed to 65kHz
with an accuracy +/-7.7% at 25
3.6
3.6.1
The complete system current loop is shown in Figure 9.
Figure 9
It consists of the current loop block which averages the
voltage at pin ISENSE, resulted from the inductor
current flowing across R1. The averaged waveform is
compared with an internal ramp in the ramp generator
and PWM block. Once the ramp crosses the average
waveform, the comparator C1 turns on the driver stage
through the PWM logic block. The Nonlinear Gain block
defines the amplitude of the inductor current. The
following sections describe the functionality of each
individual blocks.
3.6.2
The compensation of the current loop is done at the
ICOMP pin. This is the OTA2 output and a capacitor C3
has to be installed at this node to ground (see Figure
9). Under normal mode of operation, this pin gives a
voltage which is proportional to the averaged inductor
current. This pin is internally shorted to 4V in the event
of standby mode.
3.6.3
The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.
C3
ISENSE
ICOMP
R2
Full-wave
Fixed Switching Frequency
Average Current Control
Complete Current Loop
Current Loop Compensation
Pulse Width Modulation (PWM)
Retifier
ICE1PCS02/G
From
Complete System Current Loop
R1
Current Loop
1.1mS
+/-50uA (linear range)
Compensation
Current Loop
Fault
S2
OTA2
L1
4V
Functional Description
R7
o
Inductor current
proportional to
Comparator
C.
averaged
voltage
ICE1PCS02/G
PWM
D1
Nonlinear
C1
Gain
CCM-PFC
06 Feb 2007
C2
GATE
Driver
Gate
PWM Logic
R
S
R3
Voltage Loop
R4
Input From
Q
Vout