TEA1713T/N1,518 NXP Semiconductors, TEA1713T/N1,518 Datasheet - Page 15

• Manufacturer Part Number: TEA1713T/N1,518
• Description: IC CTLR RESONANT PFC 24SOIC
• Manufacturer: NXP Semiconductors

Specifications of TEA1713T/N1,518

• Package / Case: *
• Mounting Type: *
• Frequency - Switching: 125kHz
• Mode: Discontinuous Conduction (DCM)
• Switching Frequency: 125 KHz
• Maximum Power Dissipation: 0.8 W
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Current - Startup: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289598518

NXP Semiconductors
TEA1713T
Product data sheet
7.7.2.1 PFC error amplifier (pins COMPPFC and SNSBOOST)
7.7.2.2 PFC mains compensation (pin SNSMAINS)
7.7.1 PFC gate driver (pin GATEPFC)
7.7.2 PFC on-time control
The PFC controller uses valley switching to minimize losses. A primary stroke is only
started once the previous secondary stroke has ended and the voltage across the PFC
MOSFET has reached a minimum value.
The circuit driving the gate of the power MOSFET has a high current sourcing capability
I
This permits fast turn-on and turn-off of the power MOSFET to ensure efficient operation.
The driver is supplied from the regulated SUPREG supply.
The PFC operates under on-time control. The on-time of the PFC MOSFET is determined
by:
The boost voltage is divided via a high-ohmic resistive divider. It is fed to the SNSBOOST
pin. The transconductance error amplifier, which compares the SNSBOOST voltage with
an accurate trimmed reference voltage V
output current is filtered by the external loop compensation network at the COMPPFC pin.
In a typical application, the bandwidth of the regulation loop is set by a resistor and two
capacitors.
The COMPPFC voltage is clamped at a maximum of V
recovery time in the event that the boost voltage rises above the regulation level for a
period of time.
The mathematical equation for the transfer function of a power factor corrector contains
the square of the mains input voltage. In a typical application, this will result in a low
bandwidth for low mains input voltages, while at high mains input voltages the MHR
requirements may be hard to meet.
The TEA1713 contains a correction circuit to compensate for this effect. The average
mains voltage is measured via the SNSMAINS pin and this information is fed to an
internal compensation circuit.
voltage, the COMPPFC voltage, and the on-time. This compensation makes it is possible
to keep the regulation loop bandwidth constant over the full mains input range, yielding a
fast transient response on load steps, while still complying with class-D MHR
requirements.
source(GATEPFC)
•
•
The error amplifier and the loop compensation via the voltage on pin COMPPFC
At V
the on-time is at a maximum
Mains compensation via the voltage on pin SNSMAINS
ton(COMPPFC)zero
(typ. 500 mA) and a high current sink capability I
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 9 February 2011
(typ. 3.5 V), the on-time is reduced to zero. At V
Figure 7
illustrates the relationship between the SNSMAINS
reg(SNSBOOST)
Resonant power supply control IC with PFC
, is connected to this pin. The
clamp(COMPPFC)
sink(GATEPFC)
TEA1713T
. This avoids a long
© NXP B.V. 2011. All rights reserved.
ton(COMPPFC)max
(typ. 1.2 A).
15 of 47