AMIS30542C5421RG ON Semiconductor, AMIS30542C5421RG Datasheet - Page 23

• Manufacturer Part Number: AMIS30542C5421RG
• Description: IC MOTOR DVR MICRO STEP 32QFP
• Manufacturer: ON Semiconductor
• Type: Micro Stepping Motor Driverr

Specifications of AMIS30542C5421RG

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Current - Output: 2.2A
• Voltage - Supply: 6 V ~ 30 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-VSQFP
• Product: Stepper Motor Controllers / Drivers
• Operating Supply Voltage: 6 V to 30 V
• Supply Current: 8 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Examples of combined READ and WRITE
Operations
operations are combined. In Figure 22 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
back command in order to verify the data correctly written
as illustrated in Figure 23. During reception of the READ
command the old data is returned for a second time. Only
after receiving the READ command the new data is
In the following examples successive READ and WRITE
After the write operation the Master could initiate a read
Figure 21. Single WRITE Operation Where DATA from the Master is Written in SPI Register with Address 3
DO
CS
DI
DATA from previous command or
NOT VALID after POR or RESET
DATA from previous
command or NOT VALID
after POR or RESET
DO
CS
DI
Figure 22. 2 Successive READ Commands Followed by a WRITE Command
Registers are updated with the internal
status at the rising edge of the internal
AMIS−30542 clock when CS = 1
COMMAND
or NOT VALID
READ DATA
from ADDR4
OLD DATA
DATA
OLD DATA or NOT VALID
WRITE DATA to ADDR3
COMMAND
DATA
http://onsemi.com
COMMAND
from ADDR4
READ DATA
from ADDR5
DATA
DATA
23
by writing a control byte in Control Register at ADDR2.
Note that during the write command the old data of the
pointed register is returned at the moment the new data is
shifted in
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CS line is high, the first read out byte
might represent old status information.
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
OLD DATA from ADDR3
NEW DATA for ADDR3
COMMAND
WRITE DATA
from ADDR5
to ADDR 2
DATA
DATA
DATA
DATA
The NEW DATA is written into the
corresponding internal register at
the rising edge of CS
from ADDR2
NEW DATA
for ADDR2
OLD DATA
DATA
DATA