AMIS30624C6245RG ON Semiconductor, AMIS30624C6245RG Datasheet - Page 41

• Manufacturer Part Number: AMIS30624C6245RG
• Description: IC STEPPER DVR I2C 800MA 32-NQFP
• Manufacturer: ON Semiconductor
• Type: I2C Micro Stepping Motor Driverr

Specifications of AMIS30624C6245RG

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Current - Output: 800mA
• Voltage - Supply: 8 V ~ 29 V
• Operating Temperature: -40°C ~ 165°C
• Mounting Type: Surface Mount
• Package / Case: 32-VSQFP
• Product: Stepper Motor Controllers / Drivers
• Operating Supply Voltage: 8 V to 29 V
• Supply Current: 800 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 766-1002-2

AMIS-30624
15.5.3. Clock Generation
The master generates the clock on the SCK line to transfer messages on the I
clock.
15.6 Data Formats with 7-bit Addresses
Data transfers follow the format shown in Figure 29. After the START condition (S), a slave address is sent. This address is 7-bit long
followed by an eighth bit which is a data direction bit (R/W) – a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a request for
data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master.
However, if a master still wishes to communicate on the bus, it can generate a repeated START (Sr) and address another slave without
first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.
15.6.1. Data Transfer Formats
15.6.1.1 Writing Data to AMIS-30624
When writing to AMIS-30624, the master-transmitter transmits to slave-receiver and the transfer direction is not changed. A complete
transmission consists of:
Some commands for the AMIS-30624 are supporting eight bytes of data, other commands are transmitting two bytes of data. See Table
30.
SCK
SDA
• Start condition
• The slave address (7-bit)
• Read/Write bit (‘0’ = write)
• Acknowledge bit
• Any further data bytes are followed by an acknowledge bit. The acknowledge bit is used to signal a correct reception of the
• Stop condition to finish the transmission
•
data to the transmitter. In this case the AMIS-30624 pulls the SDA line to ‘0’. The AMIS-30624 reads the incoming data at SDA
on every rising edge of the SCK signal
condition
START
START
ADDRESS
S
1 - 7
Master to AMIS-30624
AMIS-30624 to Master
Slave Address
R/W
8
"0" = WRITE
ACK
9
Figure 30: Master Writing Data to AMIS-30624
R/W
Rev. 4 | Page 41 of 56 | www.onsemi.com
Figure 29: A Complete Data Transfer
A
S = Start condition
P = Stop condition
A = Acknowledge (SDA = LOW)
A = No Acknowledge (SDA = HIGH)
1 - 7
DATA
Data
N bytes + Acknowledge
8
2
C-bus. Data is only valid during the HIGH period of the
A
ACK
9
Data
1 - 7
DATA
PC20070219.3
A
PC20070217.6
8
P
ACK
9
condition
STOP
STOP