VN820-E STMicroelectronics, VN820-E Datasheet - Page 13
![IC DRIVER HIGH SIDE 9A PENTAWAT5](/photos/6/99/69949/497-5-pentawatt_series_-_vertical_sml.jpg)
VN820-E
Manufacturer Part Number
VN820-E
Description
IC DRIVER HIGH SIDE 9A PENTAWAT5
Manufacturer
STMicroelectronics
Type
High Sider
Datasheet
1.VN820PT-E.pdf
(44 pages)
Specifications of VN820-E
Input Type
Non-Inverting
Number Of Outputs
1
On-state Resistance
40 mOhm
Current - Output / Channel
9A
Voltage - Supply
5.5 V ~ 36 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Through Hole
Package / Case
Pentawatt-5 (Vertical, Bent and Staggered Leads)
Supply Voltage (min)
5.5 V
Supply Current
3.5 mA
Maximum Power Dissipation
65800 mW
Maximum Operating Temperature
+ 150 C
Mounting Style
Through Hole
Maximum Turn-off Delay Time
30000 ns
Maximum Turn-on Delay Time
30000 ns
Minimum Operating Temperature
- 40 C
Number Of Drivers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Peak Output
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
VN820-E
Table 12.
Table 13.
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
Test pulse
Output voltage > V
proper operation without replacing the device.
Output current < I
ISO T/R
7637/1
Normal operation
Current limitation
Overtemperature
3a
3b
Undervoltage
1
2
4
5
Overvoltage
Conditions
Truth table
Electrical transient requirements
+ 26.5V
+ 25V
+ 25V
- 25V
- 25V
- 4V
OL
OL
I
(1)
(1)
(1)
(1)
(1)
(1)
+ 46.5V
+ 50V
+ 50V
- 50V
- 50V
Doc ID 10890 Rev 6
- 5V
II
Input
(1)
H
H
H
H
H
H
H
H
(1)
(1)
L
L
L
L
L
L
L
(1)
(1)
(2)
+ 66.5V
- 100V
+ 75V
+ 75V
- 75V
- 6V
III
(1)
(1)
(1)
(1)
(1)
Test level
(2)
Output
+ 86.5V
+ 100V
+ 100V
- 100V
- 150V
- 7V
H
X
X
H
H
H
L
L
L
L
L
L
L
L
L
IV
(1)
(1)
(1)
(1)
(1)
(2)
Electrical specifications
Delays and impedance
100ms, 0.01
0.2ms, 10
0.1µs, 50
0.1µs, 50
400ms, 2
2ms, 10
(T
(T
j
j
Status
< T
> T
H
H
H
H
X
X
H
H
H
H
L
L
L
TSD
TSD
) H
) L
13/44