TLE6244X Infineon Technologies, TLE6244X Datasheet - Page 30

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TLE6244X

Manufacturer Part Number
TLE6244X
Description
IC LOW SIDE SWITCH 18CHAN MQFM64
Manufacturer
Infineon Technologies
Type
Low Sider
Datasheet

Specifications of TLE6244X

Input Type
SPI
Number Of Outputs
18
On-state Resistance
1 Ohm
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
64-BSQFM
Packages
PG-MQFP-64
Thermal Class
Heatslug down
Id Nom
2 x 3.0, 12 x 2.2, 4 x 1.1 A
Pin Count
64.0 Pins
Channels
18.0
Comment
injectors, solenoids, relays, general purpose
For Use With
DEMOBOARDTLE6244XIN - BOARD DEMO FOR TLE 6244X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output / Channel
-
Current - Peak Output
-
Other names
SP000013785
SP000304416
TLE6244
TLE6244
TLE6244XNT
TLE6244XT
TLE6244XXT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TLE6244X
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Company:
Part Number:
TLE6244X
Quantity:
4 800
Company:
Part Number:
TLE6244X
Quantity:
4
Final Data Sheet
1.7 µsec - Bus Interface
SSY
FCL
FDA
The µsec-bus-interface is one of three possibilities to control the power stages. OUT1...OUT7
and OUT9...OUT16 are influenced by the reset input RST. If RST is set to Low, these power
stages are switched off. After reset they are controlled by the SPI (default initialization of
TLE6244X). Power stage 8 however is not influenced by the reset input if it’s controlled by IN8
and U
the µsec-bus interface. Exception: OUT8 can be controlled by IN8 or by the SPI-interface only.
The bit ’Bus-Multiplex’ (BMUX) in the SPI register CONFIG prescribes parallel access (IN1...IN7,
IN9...IN16) or µsec-bus control (see figure below). Exception: If BMUX is set to ‘0’ only the power-
stages OUT1...OUT7 and OUT9...OUT16 are controlled by the µsec-bus.
Main features:
- 16 data bits for each data-frame (at the pin FDA)
- 16 clock-pulses for each data-frame (at the pin FCL)
- clock frequency TLE6244: 0...16 MHz
- one sync -input (pin SSY) to latch the input data stream
- input level interface same as for IN6, IN7, IN16
- no error correction
Principle of the µsec-bus interface
FDA
FCL
SSY
SPI
VDD
> 3,5V. Alternatively these outputs can be controlled either by the pins IN1...IN16 or by
Filter
Glitch
D0
16 bit shift register
16 bit µsec-bus Reg.
SCON_REG
SPI-shift-reg
D1
30
Data-Frame
INx
D14
BMUX
MUX_REG
D15
don’t care
TLE 6244X
V4.2, 2003-08-29
OUTx
D0

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