TLE6236G Infineon Technologies, TLE6236G Datasheet - Page 9

• Manufacturer Part Number: TLE6236G
• Description: IC SW SMART OCTAL LOWSIDE PDSO28
• Manufacturer: Infineon Technologies
• Type: Low Sider

Specifications of TLE6236G

• Input Type: SPI
• Number Of Outputs: 8
• On-state Resistance: 1.7 Ohm
• Current - Output / Channel: 250mA
• Current - Peak Output: 750mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-28
• Switch Type: Low Side
• Power Switch Family: TLE6236G
• Input Voltage: -0.3 to 7V
• Power Switch On Resistance: 1.7Ohm
• Output Current: 200mA
• Mounting: Surface Mount
• Supply Current: 1.5mA
• Package Type: DSO
• Operating Temperature (min): -40C
• Operating Temperature (max): 150C
• Operating Temperature Classification: Automotive
• Pin Count: 28
• Power Dissipation: 2W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: SP000012767; TLE6236GNT; TLE6236GT; TLE6236GT

SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diag-
nostic data will appear at the SO pin following the rising edge of SCLK.
switches all outputs OFF. An internal pull-up structure is provided on chip.
Diagnostics
tion as soon as an error occurs for any one of the eight channels. This fault indication can be
used to generate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called
after this fault indication. This saves processor time compared to a cyclic reading of the SO
information.
As soon as a fault occurs, the fault information is latched into the diagnosis register. Serial
data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal,
all diagnosis bits can be shifted out serially. The rising edge of CS will reset all error registers.
Logic table
Table 1: Definition of diagnostic bits under parallel and serial control
Basic principle of fault detection:
SO Bit = SI Bit:
SO Bit inverse to SI Bit :
The diagnostic bits DIAG0 to DIAG3 for channel 1 to 4 indicate a fault when the DIAG bit is
high during parallel control (IN1 .. IN4 = H; serial data bits 0 .. 3 = L). Note that the SPI serial
input (SI) bit overrides the ON state control from IN1 to IN4 regarding diagnostic information.
Compare DIAG Bit in line 3 (parallel ON only) with DIAG Bit in line 4 (serial and parallel ON)
under normal function.
Compare DIAG Bit in line 7 (parallel ON only) with DIAG Bit in line 8 (serial and parallel ON)
under fault condition.
V2.1
FAULT
RESET
1
2
3
4
5
6
7
8
Parallel
Input
- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
- Fault pin. There is a general fault pin (open drain) which shows a high to low transi-
H
H
H
H
L
L
L
L
SI Bits
0-7
H
H
H
H
L
L
L
L
SO DIAG-
Bits 0-7
Normal Function
Fault Condition
H
H
H
H
L
L
L
L
Output State
Page
OFF
OFF
ON
ON
ON
ON
ON
ON
9
Output voltage
D a t a s h e e t T L E 6 2 3 6 G
< Vref
< Vref
< Vref
< Vref
>Vref
>Vref
>Vref
>Vref
V
OUT
open load/short to gnd
Operating Mode
normal function
normal function
normal function
normal function
overload
overload
overload
26.Aug. 2002