VNN1NV04TR-E STMicroelectronics, VNN1NV04TR-E Datasheet

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... Built in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments. Fault feedback can be detected by monitoring the voltage at the input pin. Order codes Tube (lead free) Tape and reel VND1NV04-E VND1NV04TR - VNN1NV04TR - VNS1NV04TR Doc ID 7381 Rev 2 VND1NV04 OMNIFET TO-252 (DPAK ...

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Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical ...

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VND1NV04 - VNN1NV04 - VNS1NV04 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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VND1NV04 - VNN1NV04 - VNS1NV04 1 Block diagram and pin description Figure 1. Block diagram INPUT 1 Figure 2. Configuration diagram (top view) a. For the pins configuration related to SOT-223 and DPAK see outline at page 1. Gate Control ...

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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality document. Table 2. ...

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VND1NV04 - VNN1NV04 - VNS1NV04 2.2 Thermal data Table 3. Thermal data Symbol R Thermal resistance junction-case thj-case R Thermal resistance junction-lead thj-lead R Thermal resistance junction-ambient thj-amb 1. When mounted on a standard single-sided FR4 board with 50 mm ...

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Electrical specifications Table 4. Electrical characteristics (continued) Symbol Parameter t Turn-on delay time d(on) t Rise time r t Turn-off delay time d(off) t Fall time f t Turn-on delay time d(on) t Rise time r t Turn-off delay time ...

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VND1NV04 - VNN1NV04 - VNS1NV04 Figure 4. Switching time test circuit for resistive load gen 90 10 d(on) d(off) Doc ID 7381 Rev 2 Electrical specifications gen V gen t ...

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Electrical specifications Figure 5. Test circuit for diode recovery times 330Ω Figure 6. Unclamped inductive load test circuits 10/ FAST OMNIFET DIODE gen I V gen R GEN Doc ID ...

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VND1NV04 - VNN1NV04 - VNS1NV04 Figure 7. Input charge test circuit Figure 8. Unclamped inductive waveforms V GEN IN Doc ID 7381 Rev 2 Electrical specifications ND8003 11/33 ...

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Electrical specifications 2.4 Electrical characteristics curves Figure 9. Source-drain diode forward characteristics Vsd (mV) 1000 950 Vin=0V 900 850 800 750 700 (A) Figure 11. Derating curve Figure 13. Static drain-source on resistance vs. ...

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VND1NV04 - VNN1NV04 - VNS1NV04 Figure 15. Static drain-source on resistance vs. Id Rds(on) (mohms) 500 450 Tj=150ºC 400 350 300 250 Tj=25ºC 200 150 Tj=-40ºC 100 0.25 0.5 0.75 1 1.25 Id(A) Figure 17. Turn-on current ...

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Electrical specifications Figure 21. Turn-off drain-source voltage slope (part 2/2) dv/dt(V/us) 350 300 250 200 150 100 500 1000 1500 Rg(ohm) Figure 23. Switching time resistive load (part 1/2) t(us) 2 1.75 td(off) Vdd=15V 1.5 Id=0.5A Vin=5V ...

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VND1NV04 - VNN1NV04 - VNS1NV04 Figure 27. Normalized input threshold voltage vs. temperature Vinth (V) 2 1.8 Vds=Vin 1.6 Id=1mA 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 - (ºC) Figure 29. Step response ...

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Protection features 3 Protection features During normal operation, the input pin is electrically connected to the gate of the internal Power MOSFET through a low impedance path. The device then behaves like a standard Power MOSFET and can be used ...

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VND1NV04 - VNN1NV04 - VNS1NV04 4 Package and PCB thermal data 4.1 DPAK thermal data Figure 30. DPAK PC board 1. Layout condition thickness=35 µm , Copper areas: from minimum pad layout Figure 31. ...

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Package and PCB thermal data Figure 32. DPAK thermal impedance junction ambient single pulse ZTH ( ° 100 10 1 0,1 0,0001 0,001 Equation 1: pulse calculation formula ⋅ δ THδ TH where δ = ...

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VND1NV04 - VNN1NV04 - VNS1NV04 Table 5. DPAK thermal parameter Area/island (cm R1 (°C/W) R2 (°C/W) R3 (°C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W·s/°C) C2 (W·s/°C) C3 (W·s/°C) C4 (W·s/°C) C5 (W·s/°C) C6 (W·s/°C) 4.2 SOT-223 thermal data ...

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Package and PCB thermal data Figure 35. SOT-223 R 140 130 120 110 100 Figure 36. SOT-223 thermal impedance junction ambient single pulse ZTH ( ° 1000 100 10 1 0,1 0,0001 0,001 ...

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VND1NV04 - VNN1NV04 - VNS1NV04 Equation 2: pulse calculation formula ⋅ δ THδ TH where δ Figure 37. SOT-223 thermal fitting model of a single channel Table 6. SOT-223 thermal parameter Area/island (cm ...

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Package and PCB thermal data 4.3 SO-8 thermal data Figure 38. SO-8 PC board 1. Layout condition thickness=35 µm , Copper areas: from minimum pad layout Figure 39. SO-8 R 105 ...

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VND1NV04 - VNN1NV04 - VNS1NV04 Figure 40. SO-8 thermal impedance junction ambient single pulse ZTH (° 1000 100 10 1 0,1 0,0001 Equation 3: pulse calculation formula ⋅ δ THδ TH where δ ...

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Package and PCB thermal data Table 7. SO-8 thermal parameter Area/island (cm R1 (°C/W) R2 (°C/W) R3 (°C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W·s/°C) C2 (W·s/°C) C3 (W·s/°C) C4 (W·s/°C) C5 (W·s/°C) C6 (W·s/°C) 24/33 VND1NV04 - VNN1NV04 ...

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VND1NV04 - VNN1NV04 - VNS1NV04 5 Package and packing information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product ...

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Package and packing information Table 8. DPAK mechanical data Dim Package weight 26/33 VND1NV04 - VNN1NV04 - VNS1NV04 mm. Min. Typ. 2.20 ...

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VND1NV04 - VNN1NV04 - VNS1NV04 5.2 SOT-223 mechanical data Figure 43. SOT-223 mechanical data & package outline 5.3 SO8 mechanical data Table 9. SO-8 mechanical data Dim Package and packing information mm Min. Typ. 0.10 1.25 Doc ...

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Package and packing information Table 9. SO-8 mechanical data (continued) Dim ( ( ccc 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or ...

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VND1NV04 - VNN1NV04 - VNS1NV04 5.4 DPAK packing information The devices can be packed in tube or tape and reel shipments (see the page 1 ). DPAK FOOTPRINT TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, ...

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Package and packing information 5.5 SOT-223 packing information Figure 45. SOT-223 tape and reel shipment (suffix “TR”) Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter ...

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VND1NV04 - VNN1NV04 - VNS1NV04 5.6 SO8 packing information Figure 46. SO-8 tube shipment (no suffix) Figure 47. SO-8 tape and reel shipment (suffix “TR”) TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape ...

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Revision history 6 Revision history Table 10. Document revision history Date Feb-2003 16-Apr-2009 32/33 Revision 1 Initial release. Added Table 1: Device summary on page 1 and PCB thermal data 2 Updated Section 5: Package and packing information on page ...

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... VND1NV04 - VNN1NV04 - VNS1NV04 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...