MAX15019AASA+T Maxim Integrated Products, MAX15019AASA+T Datasheet - Page 10

• Manufacturer Part Number: MAX15019AASA+T
• Description: IC MOSF DRVR HALF BRDG HS 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: High Side/Low Sider

Specifications of MAX15019AASA+T

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 36ns
• Current - Peak: 3A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 125V
• Voltage - Supply: 8 V ~ 12.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width) Exposed Pad, 8-eSOIC. 8-HSOIC
• Rise Time: 50 ns
• Fall Time: 40 ns
• Supply Voltage (min): 8 V
• Supply Current: 2.75 mA
• Maximum Power Dissipation: 1904 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Bridge Type: Half Bridge
• Maximum Turn-off Delay Time: 36 ns
• Maximum Turn-on Delay Time: 36 ns
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The bootstrap capacitor is used to ensure adequate
charge is available to switch the high-side MOSFET.
This capacitor is charged from V
bootstrap diode when the low-side MOSFET is on. The
bootstrap capacitor value should be selected carefully
to avoid oscillations during turn-on and turn-off at the
DH output. Choose a capacitor value approximately 20
times greater than the total gate capacitance of the
MOSFET being switched. Use a low-ESR, X7R-type
dielectric ceramic capacitor (typically a 0.1µF ceramic
is adequate). The high-side MOSFET’s continuous on-
time is limited due to the charge loss from the high-side
driver’s quiescent current. The maximum on-time is
dependent on the size of C
V
time to charge up to V
stant of the charging loop through the lower MOSFET
(see the Typical Operating Circuit ). Ensure that the
lower MOSFET is on for at least the minimum time
required to charge C
The MAX15018_ are CMOS (V
and the MAX15019_ are TTL-compatible logic-input dri-
vers. The required logic-input levels are independent of
V
ply while the logic inputs are provided from 12V CMOS
logic. Additionally, the logic inputs are protected against
voltage spikes up to 15V, regardless of V
TTL and CMOS logic inputs have 400mV and 1.6V hys-
teresis, respectively, to avoid double pulsing during sig-
nal transition. The logic inputs are high-impedance pins
(500kΩ typ) and should not be left unconnected to
ensure the input logic state is at a known level. With the
logic inputs unconnected, the DH and DL outputs pull
low as V
PWM output from the controller must assume a proper
state while powering up the device.
Careful attention is required when choosing the bypass-
ing and grounding scheme of the MAX15018_/
MAX15019_. Peak supply and output currents may
125V/3A, High-Speed,
Half-Bridge MOSFET Drivers
10
BST_UVLO.
DD
. For example, the IC can be powered by a 10V sup-
______________________________________________________________________________________
DD
Note that the bootstrap capacitor requires
rises up above the UVLO threshold. The
Supply Bypassing and Grounding
Driver Logic Inputs (IN_H, IN_L)
Applications Information
BST
DD
.
, according to the time con-
BST
Bootstrap Capacitor
DD
, I
DD
BST
/2) logic-input drivers,
through the internal
(190µA max), and
DD
voltage. The
exceed 6A when both drivers are simultaneously driving
large external capacitive loads in phase. Supply drops
and ground shifts create forms of negative feedback for
inverterting topologies and may degrade the delay and
transition times. Ground shifts due to insufficient device
grounding may also disturb other circuits sharing the
same AC ground return path. Any series inductance in
the V
tions due to the very high di/dt when switching the
MAX15018_/MAX15019_ with any capacitive load. Place
one or more 0.1µF ceramic capacitors in parallel from
V
bypass the input supply. Use a ground plane to minimize
ground return resistance and series inductance. Place
the external MOSFETs as close as possible to the
MAX15018_/MAX15019_ to reduce trace length and fur-
ther minimize board inductance and AC path resistance.
Power dissipation in the MAX15018_/MAX15019_ is pri-
marily due to power loss in the internal boost diode and
the internal nMOS and pMOS FETS. For capacitive
loads, the total power dissipation for the device is:
where C
DL, V
frequency of the IC. P
the internal bootstrap diode (P
power dissipation reduces by P
bootstrap Schottky diode is used. The power dissipation
in the internal boost diode (when driving a capacitive
load) will be the charge through the diode per switching
period multiplied by the maximum diode forward voltage
drop (V
where C
ply voltage, f
verter, V
The total power dissipation when using the internal
boost diode will be P
Schottky diode, will be P
dissipated in the device must be kept below the maxi-
mum of 1.95W for the 8-pin SO with exposed pad at T
= +70°C ambient.
DD
P
D
DD
to GND as close as possible to the device to
DD
= (C
F
, DH, DL, and/or GND paths can cause oscilla-
F
DH
L
= 1V) as given in the following equation.
is the supply voltage, and f
P
is the maximum diode forward voltage drop.
is the combined capacitive load at DH and
DIODE
L
is the capacitive load at DH, V
x V
SW
DD
is the switching frequency of the con-
= C
2
x f
DH
D
D
SW
includes the power dissipated in
x (V
and, when using an external
) + (I
D
DD
- P
VDDO
DIODE
- 1) x f
Power Dissipation
DIODE
DIODE
SW
+ I
. The total power
SW
BSTO
is the switching
, if an external
). The internal
x V
DD
) x V
F
is the sup-
DD
A