MCZ33927EKR2 Freescale Semiconductor, MCZ33927EKR2 Datasheet - Page 23
![IC FET PRE-DRIVER 3PH 54-SOIC](/photos/15/90/159027/soic-54_sml.jpg)
MCZ33927EKR2
Manufacturer Part Number
MCZ33927EKR2
Description
IC FET PRE-DRIVER 3PH 54-SOIC
Manufacturer
Freescale Semiconductor
Specifications of MCZ33927EKR2
Configuration
3 Phase Bridge
Input Type
Inverting and Non-Inverting
Delay Time
265ns
Current - Peak
600mA
Number Of Configurations
1
Number Of Outputs
3
High Side Voltage - Max (bootstrap)
75V
Voltage - Supply
8 V ~ 40 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
VLS REGULATOR (VLS)
approximately 15V. This is an internally generated supply
from VPWR. It is the source for the low side gate drive
voltage, and also the high side bootstrap source. A low ESR
decoupling capacitor, capable of sourcing the pulsed drive
currents, must be connected between this pin and VSS or
PGND.
VPWR INPUT (VPWR)
flowing into this input recharges the bootstrap capacitors as
Analog Integrated Circuit Device Data
Freescale Semiconductor
VLS is the gate drive power supply regulated at
VPWR is the power supply input for VLS and VDD. Current
well as supplying power to the low-side gate drivers and the
VDD regulator. An internal regulator regulates the actual gate
voltages. This pin can be connected to system battery
voltage if power dissipation is not a concern.
EXPOSED PAD (EP)
heat out of the device. This pad may be connected electrically
to the substrate of the device.The device will perform as
specified with the Exposed Pad un-terminated (floating).
However, it is recommended that the Exposed Pad be
terminated to pin 29 (VSS) and the system ground.
The primary function of the Exposed Pad is to conduct
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
33927
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