MCZ33927EKR2 Freescale Semiconductor, MCZ33927EKR2 Datasheet - Page 16
![IC FET PRE-DRIVER 3PH 54-SOIC](/photos/15/90/159027/soic-54_sml.jpg)
MCZ33927EKR2
Manufacturer Part Number
MCZ33927EKR2
Description
IC FET PRE-DRIVER 3PH 54-SOIC
Manufacturer
Freescale Semiconductor
Specifications of MCZ33927EKR2
Configuration
3 Phase Bridge
Input Type
Inverting and Non-Inverting
Delay Time
265ns
Current - Peak
600mA
Number Of Configurations
1
Number Of Outputs
3
High Side Voltage - Max (bootstrap)
75V
Voltage - Supply
8 V ~ 40 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 4. Dynamic Electrical Characteristics (continued)
values noted reflect the approximate parameter means at T
16
33927
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
SPI INTERFACE TIMING
Notes
Maximum Frequency of SPI Operation
Internal Time Base
Internal Time Base drift from value at 25°C
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup Time)
SI, CS, SCLK Signal Rise Time
SI, CS, SCLK Signal Fall Time
Time from Falling Edge of CS to SO Low Impedance
Time from Rising Edge of CS to SO High Impedance
Time from Rising Edge of SCLK to SO Data Valid
Time from Rising Edge of CS to Falling Edge of the next CS
44.
45.
46.
47.
48.
Characteristics noted under conditions 8.0V ≤ V
This parameter is guaranteed by design, not production tested.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
Characteristic
(44)
(44)
,
,
(45)
(45)
(44)
(44)
(44)
(44)
(44)
(44)
,
(48)
PWR
,
,
(46)
(47)
= V
(44)
BAT
A
= 25°C under nominal conditions unless otherwise noted.
(44)
(44)
≤ 40V, -40°C ≤ T
Symbol
t
t
SIHOLD
t
t
TC
t
t
SODIS
VALID
t
SOEN
LEAD
SISU
t
f
t
f
LAG
t
RSI
FSI
OP
DT
TB
TB
A
≤ 125°C, unless otherwise noted. Typical
Min
100
100
200
13
25
25
-5
–
–
–
–
–
–
Analog Integrated Circuit Device Data
Typ
100
5.0
5.0
17
55
55
–
–
–
–
–
–
Freescale Semiconductor
Max
100
125
100
5.0
25
5
–
–
–
–
–
–
–
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%