LTC3900ES8#PBF Linear Technology, LTC3900ES8#PBF Datasheet - Page 6
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LTC3900ES8#PBF
Manufacturer Part Number
LTC3900ES8#PBF
Description
IC DRIVER RECT SYNC CONV 8SOIC
Manufacturer
Linear Technology
Datasheet
1.LTC3900ES8.pdf
(20 pages)
Specifications of LTC3900ES8#PBF
Configuration
High-Side
Input Type
Inverting and Non-Inverting
Delay Time
60ns
Current - Peak
2A
Number Of Configurations
2
Number Of Outputs
2
Voltage - Supply
4.5 V ~ 11 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
High Side Voltage - Max (bootstrap)
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
CS
Connect CS
external catch MOSFET, Q4. Connect CS
The LTC3900 monitors the CS inputs 250ns after CG goes
high. If the inductor current reverses and fl ows into the
MOSFET causing CS
10.5mV, the LTC3900 pulls CG low. See the Current Sense
section for more details on choosing the resistance value
for R
CG (Pin 3): Catch MOSFET Gate Driver. This pin drives the
gate of the external N-channel catch MOSFET, Q4.
V
ers and the rest of the internal circuitry. Bypass this pin
to GND using a 4.7μF ceramic capacitor in close proximity
to the LTC3900.
FG (Pin 5): Forward MOSFET Gate Driver. This pin drives
the gate of the external N-channel forward MOSFET, Q3.
PIN FUNCTIONS
LTC3900
BLOCK DIAGRAM
6
CC
+
, CS
(Pin 4): Main Supply Input. This pin powers the driv-
CS1
–
to R
(Pin 1, 2): Current Sense Differential Input.
+
CS3
through a series resistor to the drain of the
.
+
TIMER
to rise above CS
SYNC
CS
CS
+
–
8
1
2
7
M
TMR
10.5mV
–
+
+1.4V
–1.4V
–
–
Z
11V
to the source.
by more than
Z
0.5 • V
TMR
CS
TMR
S
S –
IS
+
CC
SYNC
SYNC
+
–
R1
180k
R2
45k
DISABLE
DRIVER
GND (Pin 6): The V
nected directly to this GND pin.
TIMER (Pin 7): Timer Input. Connect this pin to an external
R-C network to program the timeout period. The LTC3900
resets the timer at every negative transition of the SYNC
input. If the SYNC signal is missing or incorrect, the
LTC3900 pulls both CG and FG low once the TIMER pin
goes above the timeout threshold. See the Timer section
for more details on programming the timeout period.
SYNC (Pin 8): Driver Synchronization Input. This input
is signal edge sensitive. A negative voltage slew at SYNC
forces FG to pull high and CG to pull low. A positive volt-
age slew at SYNC forces FG to pull low and CG to pull
high. The SYNC input can accept both pulse or square
wave signals.
UVLO
3900 BD
DRIVER
LOGIC
SYNC
AND
TIMER
RESET
CC
bypass capacitor should be con-
4
5
3
6
V
FG
CG
GND
CC
3900fa