ICB1FL02G Infineon Technologies, ICB1FL02G Datasheet - Page 16

• Manufacturer Part Number: ICB1FL02G
• Description: IC SMART BALLAST CONTROL PDSO-18
• Manufacturer: Infineon Technologies
• Type: PFC/Ballast Controllerr

Specifications of ICB1FL02G

• Frequency: 20 ~ 100 kHz
• Current - Supply: 650µA
• Voltage - Supply: 10.5 V ~ 17.5 V
• Operating Temperature: -25°C ~ 125°C
• Package / Case: DSO-18
• Packages: PG-DSO-18
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Lead Free Status / Rohs Status: Details
• Other names: ICB1FL02GXT; SP000204703

A second threshold detects severe deviations such as rectangular shapes of voltage during operation below
resonance (CapLoad2). Then the inverter is turned off as soon as these conditions last longer than 610µs and the
IC changes over into fault mode. The evaluation of the failure condition is done by an up and down counter which
samples the status every 40µs.
CapLoad1 is sensed in the moment when low-side Gate drive is turned on. If the voltage level at pin RES is above
the V
CapLoad2 is sensed in the moment when the high-side Gate drive is turned on. If the voltage level at pin RES is
below the V
level V
D10 limits voltage transients at pin RES that can occur during removal of the lamp in run mode.
Figure 14
3.6
In the event of a failing operation the fault latch is set after the specified reaction time (e.g. 500ms at EOL2). Then
the Gate drives are shut down immediately, the control functions are disabled and the current consumption is
reduced to a level of 150µA (typically). Vcc is clamped by internal zener diode to max 17,5V at 2mA. So the
internal zener diode is only designed to limit Vcc when fed from the start-up current, but not from the charge pump
supply! There is a current limitation at the internal zener diode function (max 5mA at Vcc= 17,5V) in order to avoid
conflicts with the clamping level of the external zener diode.
The capacitor at pin RES is discharged and charged during 32 cycles in order to generate a delay of several 10ms.
The delay is implemented for avoiding malfunctions in detecting the lamp removal due to voltage transients that
can occur after shut down. The reset of the fault latch happens after exceeding the 1,6V threshold at pin RES and
enabling the IC after lamp removal and subsequent decreasing voltage level at pin RES below the 1,3V threshold.
Datasheet Version 2.1
REScap
RESLLV
Interruption of Operation and Restart after Lamp Removal
threshold (typ. 0,24V) related to the level V
REScap
is a floating level, it is updated every on-time of the low-side MOSFET.
Levels and points in time for detection of CapLoad1 and CapLoad2.
Gate HS
Gate LS
V
V
threshold related to the level V
RESCAP
RESLLV
V
V
I
DSLS
DLS
RES
t
CAPM
1
RESLLV
RESLLV
16
, conditions of CapLoad2 are assumed. As the reference
Deadtime
, conditions of CapLoad1 are assumed.
t
CAPM
2
Functional Description
t
t
t
t
September 2008
ICB1FL02G