PCA9553D/01,112 NXP Semiconductors, PCA9553D/01,112 Datasheet - Page 9

• Manufacturer Part Number: PCA9553D/01,112
• Description: IC LED DRIVER LINEAR 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: Linear (I²C Interface)r

Specifications of PCA9553D/01,112

• Package / Case: 8-SOIC (3.9mm Width)
• Topology: Open Drain, PWM
• Number Of Outputs: 4
• Internal Driver: Yes
• Type - Primary: LED Blinker
• Frequency: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 25mA
• Internal Switch(s): Yes
• Low Level Output Current: 25 mA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Supply Current: 500 uA
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Efficiency: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-3390-5; 935272825112; PCA9553D/01

NXP Semiconductors
PCA9553_6
Product data sheet
Fig 10. System configuration
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
8.2 System configuration
8.3 Acknowledge
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 9.
SDA
SCL
RECEIVER
Definition of START and STOP conditions
SLAVE
START condition
S
Rev. 06 — 29 December 2008
TRANSMITTER/
RECEIVER
SLAVE
4-bit I
Figure
2
C-bus LED driver with programmable blink rates
TRANSMITTER
10).
MASTER
TRANSMITTER/
RECEIVER
MASTER
SLAVE
STOP condition
P
MULTIPLEXER
PCA9553
© NXP B.V. 2008. All rights reserved.
I
2
C-BUS
002aaa966
mba608
SDA
SCL
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