PCA9532PW,118 NXP Semiconductors, PCA9532PW,118 Datasheet - Page 18
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PCA9532PW,118
Manufacturer Part Number
PCA9532PW,118
Description
IC LED DRIVER RGB 24-TSSOP
Manufacturer
NXP Semiconductors
Type
RGB LED Driverr
Datasheet
1.PCA9532BS118.pdf
(29 pages)
Specifications of PCA9532PW,118
Package / Case
24-TSSOP
Topology
Open Drain, PWM
Number Of Outputs
16
Internal Driver
Yes
Type - Primary
Backlight, LED Blinker
Type - Secondary
RGB
Frequency
400kHz
Voltage - Supply
2.3 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Current - Output / Channel
25mA
Internal Switch(s)
Yes
Low Level Output Current
25 mA
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Supply Current
550 uA
Maximum Power Dissipation
400 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Output
-
Efficiency
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
935272837118
PCA9532PW-T
PCA9532PW-T
PCA9532PW-T
PCA9532PW-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9532PW,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
11. Dynamic characteristics
Table 14.
[1]
[2]
[3]
[4]
[5]
PCA9532_4
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing
t
t
t
Reset
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
r
f
SP
v(Q)
su(D)
h(D)
w(rst)
rec(rst)
rst
t
t
C
Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
Upon reset, the full delay will be the sum of t
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
= minimum time for SDA data output to be valid following SCL LOW.
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Dynamic characteristics
Parameter
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
data output valid time
data input set-up time
data input hold time
reset pulse width
reset recovery time
reset time
rst
and the RC time constant of the SDA bus.
Rev. 04 — 17 March 2009
Conditions
LOW-level
HIGH-level
[4][5]
[1]
[2]
[2]
Standard-mode
Min
250
100
400
4.7
4.0
4.7
4.0
4.7
4.0
10
0
0
1
0
-
-
-
-
-
-
-
I
2
C-bus
1500
1000
Max
100
600
600
300
200
50
-
-
-
-
-
-
-
-
-
-
-
-
-
16-bit I
20 + 0.1C
20 + 0.1C
Fast-mode I
Min
100
100
400
1.3
0.6
0.6
0.6
1.3
0.6
10
0
0
1
0
-
-
-
-
-
2
C-bus LED dimmer
PCA9532
b
b
© NXP B.V. 2009. All rights reserved.
[3]
[3]
2
C-bus
Max
400
600
600
600
300
300
200
50
-
-
-
-
-
-
-
-
-
-
-
-
-
18 of 29
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s