PCA9624PW,118 NXP Semiconductors, PCA9624PW,118 Datasheet
PCA9624PW,118
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PCA9624PW,118 Summary of contents
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PCA9624 8-bit Fm+ I Rev. 02 — 26 August 2009 1. General description The PCA9624 dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM ...
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... NXP Semiconductors 2. Features I 8 LED drivers. Each output programmable at: N Off Programmable LED brightness N Programmable group dimming/blinking mixed with individual LED brightness I 1 MHz Fast-mode Plus compatible I on SDA output for driving high capacitive buses I 256-step (8-bit) linear programmable brightness per LED output varying from fully off ...
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... NXP Semiconductors 3. Applications I RGB or RGBA LED drivers I LED status information I LED displays I LCD backlights I Keypad backlights for cellular phones or handheld devices 4. Ordering information Table 1. Ordering information Type number Topside mark PCA9624BS 9624 PCA9624PW PCA9624PW PCA9624_2 Product data sheet Package Name Description HVQFN24 plastic thermal enhanced very thin quad fl ...
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PCA9624 SCL INPUT FILTER SDA POWER- RESET V SS PWM REGISTER X BRIGHTNESS CONTROL 24.3 kHz 97 kHz 25 MHz OSCILLATOR OE Remark: Only one LED output shown for clarity. Fig 1. Block diagram of PCA9624 A0 A1 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning LED0 LED1 LED2 LED3 V SS Fig 2. 6.2 Pin description Table 2. Symbol LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 SCL SDA V DD PCA9624_2 Product data sheet SDA 3 22 SCL PCA9624PW LED7 9 16 LED6 10 15 LED5 ...
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... NXP Semiconductors [1] HVQFN24 package supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.1.2 LED All Call I • Default power-up value (ALLCALLADR register): E0h or 1110 000 • Programmable through I • ...
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... NXP Semiconductors 7.2 Control register Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address, the bus master will send a byte to the PCA9624, which will be stored in the Control register. The lowest 5 bits are used as a pointer to determine which register will be accessed (D[4:0]). The highest 3 bits are used as Auto-Increment fl ...
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... NXP Semiconductors AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I blinking change. AI[2:0] = 111 is used when individual and global changes must be performed during the 2 same I same time. Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits. ...
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... NXP Semiconductors 7.3.1 Mode register 1, MODE1 Table 5. Legend: * default value. Bit Symbol 7 AI2 6 AI1 5 AI0 4 SLEEP 3 SUB1 2 SUB2 1 SUB3 0 ALLCALL [1] It takes 500 s max. for the oscillator and running once SLEEP bit has been set to logic 1. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window ...
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... NXP Semiconductors 7.3.3 PWM0 to PWM7, individual brightness control Table 7. Legend: * default value. Address 02h 03h 04h 05h 06h 07h 08h 09h A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99 ...
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... NXP Semiconductors 7.3.5 GRPFREQ, group frequency Table 9. Legend: * default value. Address 0Bh GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3 registers) ...
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... NXP Semiconductors 7.3.7 SUBADR1 to SUBADR3, I Table 11. Legend: * default value. Address 0Eh 0Fh 10h Subaddresses are programmable through the I E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1 register is equal to 0). Once subaddresses have been programmed to their right values, SUBx bits need to be set to logic 1 in order to have the device acknowledging these addresses (MODE1 register) ...
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... NXP Semiconductors 7.4 Active LOW output enable input The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at the same time. • When a LOW level is applied to OE pin, all the LED outputs are enabled. • When a HIGH level is applied to OE pin, all the LED outputs are high-impedance. ...
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... NXP Semiconductors b. Byte 2 = 5Ah: the PCA9624 acknowledges this value only. If byte 2 is not equal to 5Ah, then the PCA9624 does not acknowledge it. If more than 2 bytes of data are sent, the PCA9624 does not acknowledge any more. 5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 10. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 9. Bus transactions slave address START condition (1) See Table 4 for register definition. Fig 12. Write to a specific register slave address START condition R/W acknowledge from slave SUBADR3 register (cont.) A acknowledge from slave Fig 13. Write to all registers using the Auto-Increment feature ...
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... NXP Semiconductors slave address START condition R/W acknowledge from slave data from MODE2 register (cont.) A acknowledge from master data from last read byte (cont not acknowledge STOP from master condition Fig 15. Read all registers using the Auto-Increment feature slave address sequence (A) ...
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... NXP Semiconductors 10. Application design-in information V = 2 C-BUS/SMBus MASTER SDA SCL OE (1) OE requires pull-up resistor if control signal from the master is open-drain C-bus address = 0010 101x. Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated. Consider disabling LED outputs using HIGH level applied to OE pin. ...
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... NXP Semiconductors 10.1 Junction temperature calculation A device junction temperature can be calculated when the ambient temperature or the case temperature is known. When the ambient temperature is known, the junction temperature is calculated using Equation 4 power dissipation amb where junction temperature j T amb R th(j- (device) total power dissipation ...
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... NXP Semiconductors 10.1.1 Example known R th(j-a) T amb LED output low voltage (LED V LED output current per channel = 80 mA Number of outputs = 8 I DD(max) V DD(max C-bus clock (SCL) maximum sink current = C-bus data (SDA) maximum sink current = Find P – output total power = 80 mA – ...
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... NXP Semiconductors 1. Find P – output current (60 mA – output current (50 mA – output current (40 mA – output current (20 mA – output current (1 mA Output total power = 341.5 mW – chip core power consumption = 18 mA – SCL power dissipation = 25 mA – SDA power dissipation = 25 mA ...
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... NXP Semiconductors Table 14. Measurement amb maximum power dissipation (chip + output drivers) maximum power dissipation (output drivers only) maximum drive current per channel amb maximum power dissipation (chip + output drivers) maximum power dissipation (output drivers only) maximum drive current per channel amb ...
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... NXP Semiconductors 13. Static characteristics Table 16. Static characteristics Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current ...
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... NXP Semiconductors [3] Tested with outputs off 4.5 V (A) 3.0 V 0.25 2.3 V 0.15 0.05 0.05 0.05 0. amb amb Fig 18. V versus PCA9624_2 Product data sheet 002aae510 0. (A) 0.15 0.05 0.05 0.35 0. (A) 4.5 V 3.0 V 0.15 2.3 V 0.05 0.05 0.05 ...
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... NXP Semiconductors 14. Dynamic characteristics Table 17. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a BUF STOP and START condition t hold time (repeated) HD;STA START condition t set-up time for a SU;STA repeated START condition t set-up time for STOP SU;STO condition ...
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... NXP Semiconductors [ minimum time for SDA data out to be valid following SCL LOW. VD;DAT [3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V bridge the undefined region of SCL’s falling edge. [4] The maximum t for the SDA and SCL bus lines is specifi ...
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... NXP Semiconductors 15. Test information Fig 21. Test circuitry for switching times PCA9624_2 Product data sheet V I PULSE GENERATOR R = Load resistor for LEDn. R for SDA and SCL > less current Load capacitance includes jig and probe capacitance Termination resistance should be equal to the output impedance Z T Rev. 02 — ...
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... NXP Semiconductors 16. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 20. Acronym CDM DUT ESD FET HBM 2 I C-bus I/O LCD LED LSB ...
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... NXP Semiconductors Table 20. Acronym RGB RGBA SMBus 20. Revision history Table 21. Revision history Document ID Release date PCA9624_2 20090826 • Modifications: Section 7.4 “Active LOW output enable • Figure 17 “Typical • Added (new) • Section 11 “Limiting – Table 13 “Limiting – Added (new) capability” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 6 2 7.1.1 Regular I C-bus slave address . . . . . . . . . . . . . 6 2 7.1.2 LED All Call I C-bus address . . . . . . . . . . . . . . ...