PCA9551PW,112 NXP Semiconductors, PCA9551PW,112 Datasheet - Page 15

• Manufacturer Part Number: PCA9551PW,112
• Description: IC LED DRIVER BLINKER 16-TSSOP
• Manufacturer: NXP Semiconductors
• Type: LED Blinkerr

Specifications of PCA9551PW,112

• Package / Case: 16-TSSOP
• Topology: Open Drain, PWM
• Number Of Outputs: 8
• Internal Driver: Yes
• Type - Primary: LED Blinker
• Frequency: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 25mA
• Internal Switch(s): Yes
• Low Level Output Current: 6.5 mA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C568-3615 - DEMO BOARD I2C
• Voltage - Output: -
• Efficiency: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1048-5; 935271692112; PCA9551PW

NXP Semiconductors
11. Dynamic characteristics
Table 13.
[1]
[2]
[3]
[4]
[5]
PCA9551_8
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing
t
t
t
Reset timing
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
r
f
SP
v(Q)
su(D)
h(D)
w(rst)
rec(rst)
rst
t
t
C
Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
Upon reset, the full delay will be the sum of t
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
= minimum time for SDA data output to be valid following SCL LOW.
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Dynamic characteristics
Parameter
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
data output valid time
data input set-up time
data input hold time
reset pulse width
reset recovery time
reset time
rst
and the RC time constant of the SDA bus.
Rev. 08 — 31 July 2008
Conditions
LOW-level
HIGH-level
8-bit I
2
C-bus LED driver with programmable blink rates
[4][5]
[1]
[2]
[2]
Standard-mode
Min
250
100
400
4.7
4.0
4.7
4.0
4.7
4.0
0
0
1
8
0
-
-
-
-
-
-
-
I
2
C-bus
1500
1000
Max
100
600
600
300
200
50
-
-
-
-
-
-
-
-
-
-
-
-
-
20 + 0.1C
20 + 0.1C
Fast-mode I
Min
100
100
400
1.3
0.6
0.6
0.6
1.3
0.6
0
0
1
8
0
-
-
-
-
-
PCA9551
b
b
© NXP B.V. 2008. All rights reserved.
[3]
[3]
2
C-bus
Max
400
600
600
600
300
300
200
50
-
-
-
-
-
-
-
-
-
-
-
-
-
15 of 26
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s