MAX5970ETX+ Maxim Integrated Products, MAX5970ETX+ Datasheet - Page 37

• Manufacturer Part Number: MAX5970ETX+
• Description: IC CTLR HOT-SWAP DUAL 36TQFN
• Manufacturer: Maxim Integrated Products
• Type: Hot-Swap Controllerr

Specifications of MAX5970ETX+

• Applications: General Purpose, PCI Express
• Internal Switch(s): No
• Voltage - Supply: 2.7 V ~ 16 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0V to 16V, Dual Hot-Swap Controller with 10-Bit
The 2-wire communication is fully compatible with exist-
ing 2-wire serial interface systems; Figure 4 shows the
interface timing diagram. The MAX5970 is a transmit/
receive slave-only device, relying upon a master device
to generate a clock signal. The master device (typically
a microcontroller) initiates data transfer on the bus and
generates SCL to permit that transfer.
A master device communicates to the MAX5970 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed by
a START (S) or REPEATED START (Sr) condition and a
STOP (P) condition. Each word transmitted over the bus
Figure 4. Serial-Interface Timing Details
Figure 5. Bit Transfer
Current and Voltage Monitor and 4 LED Drivers
t
SDA
SCL
HD:STA
SDA
SCL
CONDITION
DATA LINE STABLE,
START
DATA VALID
t
SU:DAT
______________________________________________________________________________________
t
LOW
DATA ALLOWED
CHANGE OF
t
R
t
HIGH
t
F
t
HD:DAT
t
SU:STA
REPEATED START
CONDITION
Figure 6. START and STOP Conditions
is 8 bits long and is always followed by an acknowledge
pulse.
SCL is a logic input, while SDA is a logic input/open-
drain output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7kI
for most applications.
Each clock pulse transfers one data bit. The data
on SDA must remain stable while SCL is high (see
Figure 5), otherwise the MAX5970 registers a START or
STOP condition (see Figure 6) from the master. SDA and
SCL idle high when the bus is not busy.
SDA
SCL
CONDITION
START
t
HD:STA
S
t
SU:STO
CONDITION
STOP
t
BUF
Bit Transfer
CONDITION
START
CONDITION
STOP
P
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