MAX5970ETX+ Maxim Integrated Products, MAX5970ETX+ Datasheet - Page 13

• Manufacturer Part Number: MAX5970ETX+
• Description: IC CTLR HOT-SWAP DUAL 36TQFN
• Manufacturer: Maxim Integrated Products
• Type: Hot-Swap Controllerr

Specifications of MAX5970ETX+

• Applications: General Purpose, PCI Express
• Internal Switch(s): No
• Voltage - Supply: 2.7 V ~ 16 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0V to 16V, Dual Hot-Swap Controller with 10-Bit
Table 1a. Register Address Map (Channel Specific) (continued)
Table 1b. Register Address Map (General)
mon_range
cbuf_chx_store
ifast2slow
status0
status1
status2
status3
fault0
fault1
fault2
pgdly
fokey
foset
chxen
dgl_i
dgl_uv
dgl_ov
cbufrd_hibyonly
cbuf_dly_stop
peak_log_rst
peak_log_hold
Current and Voltage Monitor and 4 LED Drivers
ov2thr_chx_msb
ov2thr_chx_ lsb
cubf_ba_chx_v
oithr_chx_msb
cubf_ba_chx_i
REGISTER
oithr_chx_ lsb
dac_chx-fast
REGISTER
______________________________________________________________________________________
MON input range setting
Selective enabling of circular buffer
Current threshold fast-to-slow ratio setting
Slow-trip and fast-trip comparators status register
PROT, MODE, and ON_ inputs status register
Fast-trip threshold maximum range setting bits, from IRNG_
three-state inputs
LATCH, POL, ALERT, and PG_ status register
Status register for undervoltage detection (warning or critical)
Status register for overvoltage detection (warning or critical)
Status register for overcurrent detection (warning)
Delay setting between MON measurement and PG_ assertion
Load register with 0xA5 to enable force-on function
Register that enables force-on function for a channel
Channel enable bits
OC deglitch enable bits
UV deglitch enable bits
OV deglitch enable bits
Circular buffers readout mode: 8 bit or 10 bit
Circular buffer stop-delay. Number of samples recorded to the
circular buffer after channel shutdown.
Reset control bits for peak-detection registers
Hold control bits for peak-detection registers
High 8 bits ([9:2]) of overvoltage critical
(OV2) threshold
Low 2 bits ([1:0]) of overvoltage critical
(OV2) threshold
High 8 bits ([9:2]) of overcurrent warning
threshold
Low 2 bits ([1:0]) of overcurrent warning
threshold
Fast-comparator threshold DAC setting
Base address for block read of 50-sample
voltage-signal data buffer
Base address for block read of 50-sample
current-signal data buffer
DESCRIPTION
DESCRIPTION
CHANNEL 1
0x20
0x21
0x22
0x23
0x2E
0x46
0x47
(HEX CODE)
ADDRESS
CHANNEL 2
0x3A
0x3B
0x3C
0x3D
0x18
0x19
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3E
0x3F
0x40
0x41
0x42
0x2A
0x2B
0x2C
0x2D
0x2F
0x48
0x49
VALUE
RESET
VALUE
RESET
0x00
0x0F
0x0F
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0F
0x19
0x00
0x00
0xBF
0xFF
0x03
0xFF
0x03
—
—
—
—
—
—
WRITE
READ/
WRITE
READ/
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/C
R/C
R/C
R
R
R
R
R
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