LTC4252A-2IMS#TRPBF Linear Technology, LTC4252A-2IMS#TRPBF Datasheet - Page 20

• Manufacturer Part Number: LTC4252A-2IMS#TRPBF
• Description: IC CNTRLR HOTSWAP NEGVOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252A-2IMS#TRPBF

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
Approximating a linear charging rate as I
I
can be approximated with 0.5 • I
equation, TIMER capacitor C
Returning to Equation (3), the TIMER period is calcu-
lated and used in conjunction with V
I
tive MOSFET.
As a numerical design example, consider a 30W load,
which requires 1A input current at 36V. If V
= 72V and C
= 40mΩ; Equation (13) gives C
errors in R
(4V), R
clamp (V
by 1.5, giving the nearest standard value of C
If a short-circuit occurs, a current of up to 120mV/40mΩ = 3 A
will flow in the MOSFET for 5.6ms as dictated by C
in Equation (3). The MOSFET must be selected based on
this criterion. The IRF530S can handle 100V and 3A for
10ms and is safe to use in this application.
Computing the maximum soft-start capacitor value during
soft-start to a load short is complicated by the nonlinear
MOSFET’s SOA characteristics and the R
An overly conservative but simple approach begins with
the maximum circuit breaker current, given by:
where V
From the SOA curves of a prospective MOSFET, determine
the time allowed, t
In the above example, 60mV/40mΩ gives 1.5A. t
for the IRF530S is 40ms. From Equation (15), C
437nF . Actual board evaluation showed that C
20
DRN(MAX)
SHORTCIRCUIT(MAX)
I
C
C
CB(MAX)
SS
T
=
=
D
t
CB(MAX)
CL(CHARGE)
, DRAIN current multiplier and DRAIN voltage
DRNCL
0.916 •R
t
S
to zero, the I
SOA(MAX)
, C
=
L
V
T
= 100μF , R
), the calculated value should be multiplied
CB(MAX)
, TIMER current (230μA), TIMER threshold
R
= 60mV (55mV for the LTC4252A).
S
SS
SOA(MAX)
to check the SOA curves of a prospec-
• 230μA + 4 •I
(
DRN
D
4V
= 1MΩ, Equation (8) gives R
. C
T
component in Equation (3)
SS
is given by:
T
is given by:
= 441nF . To account for
DRN(MAX)
DRN(MAX)
SUPPLY(MAX)
SS
DRN
C
. Rearranging
SS
)
SUPPLY(MAX)
drops from
T
SS
response.
= 680nF .
T
SOA(MAX)
= 680nF
= 100nF
SS
(13)
(14)
(15)
and
=
S
was appropriate. The ratio (R
a good gauge as a large ratio may result in the time-out
period expiring. This gauge is determined empirically with
board level evaluation.
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 2 with the LTC4252A. It was designed
for 80W.
Calculate the maximum load current: 80W/43V = 1.86A;
allowing for 83% converter efficiency, I
Calculate R
Calculate I
Select a MOSFET that can handle 3.3A at 71V: IRF530S.
Calculate C
C
t = 5.6ms.
Consult MOSFET SOA curves: the IRF530S can handle 3.3A
at 100V for 8.2ms, so it is safe to use in this application.
Calculate C
C
FREQUENCY COMPENSATION
The LTC4252A typical frequency compensation network for
the analog current limit loop is a series R
connected to V
the compensation capacitor C
The line in Figure 7 is used to select a starting value for C
based upon the MOSFET’s C
values for C
Differences in the optimized value of C
value are small. Nevertheless, compensation values should
be verified by board level short-circuit testing.
T
SS
= 680nF , which gives the circuit breaker time-out period
I
SHORTCIRCUIT(MAX)
= 68nF .
SHORTCIRCUIT(MAX)
S
T
SS
: from Equation (8) R
C
: from Equation (13) C
: using Equations (14) and (15) select
EE
are shown for several popular MOSFETs.
. Figure 7 depicts the relationship between
=
20mΩ
66mV
: from Equation (10)
ISS
SS
C
=3.3A
and the MOSFET’s C
specification. Optimized
• C
S
= 20mΩ.
SS
C
T
) to t
versus the starting
IN(MAX)
= 322nF . Select
C
(10Ω) and C
CL(CHARGE)
= 2.2A.
425212fc
ISS
is
C
C
.