LTC4212CMS Linear Technology, LTC4212CMS Datasheet - Page 12

• Manufacturer Part Number: LTC4212CMS
• Description: IC CTRLR HOTSWAP TIMEOUT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4212CMS

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.5 V ~ 16.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OPERATIO
LTC4212
Since the PGT is pulled to GND by M12 before the power
good circuit is enabled, the first positive ramp at the PGT
pin starts from 0V instead of the 0.65V for the subsequent
13 cycles.
Power Good Time-Out
At the end of the time-out period, the PGI pin is sampled.
M12 is turned on to discharge C
pin is low when sampled, the DC/DC converters have not
entered into regulation on time and the power good circuit
trips the circuit breaker to latch off the board. If PGI is high
when sampled, the converters powered up into regulation
on time and the board is left powered up. The power good
glitch filter is enabled and it monitors the PGI pin for a low,
an indication that at least one DC/DC converter has dropped
out of regulation. The glitch filter rejects low pulses
shorter than a programmable period.
Power Good Glitch Filter
A glitch filter consisting of COMP5, M5 and a 5 A current
source rejects PGI low pulses that are shorter than the
duration programmed by an external capacitor, C
connected from the PGF pin to GND.
Once the glitch filter is enabled, M5 is switched off
whenever PGI goes low. This allows an internal 5 A
current source to charge the capacitor at the PGF pin. If
PGI stays low for long enough, the voltage at the PGF pin
rises above the upper threshold of COMP5 (1.236V) and
causes the power good circuit to trip the circuit breaker.
For a given C
GND, the minimum low PGI pulse width needed to trip the
circuit breaker is given by:
An internal 5pF capacitor and stray MSOP-10 package
capacitance sets t
ted. Table 3 shows t
capacitors. Tying the PGF pin to ground prevents the
power good glitch filter from tripping the circuit breaker
after normal power-up.
12
t
PGF
= 1.236V • (C
PGF
capacitance connected between PGF and
U
PGF
PGF
to 5 s nominal when C
PGF
)/5 A + 5 s
values for various standard
PGT
to ground. If the PGI
PGF
is omit-
PGF
(4)
,
Table 3. t
Soft-Start or Inrush Current Control
The LTC4212 monitors the load current by sensing the
voltage (V
sense resistor (R
SENSE pins. During the second timing cycle (see Normal
Operating Sequence) a soft-start circuit turns on the
external N-channel FET gradually to keep inrush currents
in check. The soft-start circuit monitors and servos the
voltage across R
10 A pull-up current source to the GATE pin when the
voltage across R
with a 10 A pull-down current source when the voltage
rises above 50mV. Therefore, the inrush current from the
backplane supply is limited to:
For example, I
Assuming that the voltage across the sense resistor does
not exceed 50mV, the voltage at the GATE pin rises at rate
given by:
where, C
(C
For example, an Si4410DY (a 30V N-channel power
MOSFET) exhibits an approximate C
ISS
I
V
LIMIT(SOFTSTART)
GATE
).
PGF
GATE
Slew Rate = dV
CC
vs C
100pF
220pF
330pF
470pF
680pF
820pF
C
10pF
22pF
33pF
47pF
68pF
82pF
1nF
LIMIT(SOFTSTART)
—
PGF
– V
= Power MOSFET gate input capacitance
PGF
SENSE
SENSE
SENSE
SENSE
= 50mV/R
is less than 50mV or discharging it
) connected between the V
) developed across an external
to 50mV by either connecting a
GATE
/dt =10 A/C
= 5A when R
SENSE
GATE
121.2 s
10.4 s
13.2 s
16.6 s
21.8 s
25.2 s
29.7 s
59.3 s
86.6 s
173 s
208 s
252 s
7.5 s
GATE
t
5 s
SENSE
PGF
of 3300pF at
= 0.01 .
CC
and
4212f
(5)
(6)