LTC4257CDD#TR Linear Technology, LTC4257CDD#TR Datasheet - Page 6
![IC CONTROLLER POE INTERFACE 8DFN](/photos/7/2/70256/161-8-dfn_sml.jpg)
LTC4257CDD#TR
Manufacturer Part Number
LTC4257CDD#TR
Description
IC CONTROLLER POE INTERFACE 8DFN
Manufacturer
Linear Technology
Type
Power over Ethernet Switch (PoE)r
Datasheet
1.LTC4257CS8PBF.pdf
(20 pages)
Specifications of LTC4257CDD#TR
Applications
IP Phones, Power over LAN, Network Routers and Switches
Internal Switch(s)
Yes
Current Limit
350mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-WFDFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
APPLICATIO S I FOR ATIO
LTC4257
The LTC4257 is intended for use as the front end of a
Powered Device (PD) designed to IEEE 802.3af draft
standard. The LTC4257 includes a trimmed 25k signature
resistor, classification current source, and an inrush cur-
rent limit circuit. With these functions integrated into the
LTC4257, the signature and power interface for a PD that
meets all the requirements of IEEE 802.3af can be built
with a minimum of external components.
Using an LTC4257 for the power and signature interface
functions of a PD provides several advantages. The
LTC4257 current limit circuit includes an onboard, 100V,
400mA power MOSFET with low leakage. This onboard
low leakage MOSFET avoids the possibility of corrupting
the 25k signature resistor while also saving board space
and cost. In addition, the IEEE 802.3af inrush current limit
requirement causes large transient power dissipation in
the PD; the LTC4257 manages this turn-on sequence
through the use of smart thermal protection circuitry. The
LTC4257 is designed to allow multiple turn-on sequences
without overheating the miniature 8-lead package. In the
event of excessive power cycling, the LTC4257 provides
thermally activated current-limit reduction to keep the
onboard power MOSFET within its safe operating area.
Operation
The LTC4257 has several modes of operation depending
on the applied input voltage as shown in Figure 1 and
summarized in Table 1. These various modes satisfy the
requirements defined in the IEEE 802.3af specification.
The input voltage is applied to the V
reference to the GND pin. This input voltage is always
negative. To avoid confusion, voltages in this data sheet
are always referred to in terms of absolute magnitude.
Terms such as maximum negative voltage refer to the
largest negative voltage and a rising negative voltage
refers to a voltage that is becoming more negative. Refer-
ences to electrical parameters in this applications section
use the nominal value. Refer to the Electrical Characteris-
tics section for the range of values a particular parameter
will have.
6
U
U
W
IN
pin and is with
U
PSE
Figure 1. Output Voltage, PWRGD and PD Current
as a Function of Input Voltage
V
IN
I
I
CLASS
R
LIMIT
–20
–30
–40
–50
–20
–30
–40
–50
–20
–30
–40
–50
–10
–10
–10
CLASS
I
IN
I
I
I
I
I
1
2
CLASS
LIMIT
LOAD
=
=
2
4
V1 – 2 DIODE DROPS
V2 – 2 DIODE DROPS
UVLO
= 350mA (NOMINAL)
=
OFF
DEPENDENT ON R
dV
dt
R
V
R
POWER
DETECTION V1
CLASS
IN
LTC4257
V
LOAD
=
BAD
DETECTION V2
DETECTION I
IN
DETECTION I
I
PWRGD
LIMIT
CLASSIFICATION
I
25kΩ
25kΩ
C1
CLASS
CLASSIFICATION
V
GND
OUT
UVLO
TURN-ON
UVLO
POWER
ON
8
6
5
GOOD
2
1
CLASS
R9 R
SELECTION
PWRGD TRACKS
V
UVLO
TURN-OFF
CURRENT
LIMIT, I
LOAD CURRENT, I
τ = R
IN
POWER
LOAD
UVLO
C1
BAD
OFF
LOAD
TIME
TIME
TIME
LIMIT
4257 F01
C1
V
OUT
GND
LOAD
4257fb