LTC4261CUFD#PBF Linear Technology, LTC4261CUFD#PBF Datasheet - Page 20
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LTC4261CUFD#PBF
Manufacturer Part Number
LTC4261CUFD#PBF
Description
IC CTRLR HOTSWAP W/ADC 24-QFN
Manufacturer
Linear Technology
Type
Hot-Swap Controllerr
Datasheet
1.LTC4261IGNPBF.pdf
(32 pages)
Specifications of LTC4261CUFD#PBF
Applications
General Purpose
Internal Switch(s)
No
Voltage - Supply
9 V ~ 11.2 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-WFQFN Exposed Pad
Family Name
LTC4261
Package Type
QFN EP
Operating Supply Voltage (min)
-12V
Operating Supply Voltage (max)
-100V
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Product Depth (mm)
4mm
Product Length (mm)
5mm
Mounting
Surface Mount
Pin Count
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
LTC4261/LTC4261-2
APPLICATIONS INFORMATION
the lower address wins arbitration and responds fi rst. The
ALERT line will also be released if the device is addressed
by the bus master.
Once the ALERT signal has been released for one fault,
it will not be pulled low again until the FAULT register
indicates a different fault has occurred, or the original
fault is cleared and it occurs again. Note that this means
repeated or continuing faults will not generate alerts until
the associated FAULT register bit has been cleared.
Resetting Faults
Faults are reset with any of the following conditions.
First, writing zeros to the FAULT register B will clear the
associated fault bits. Second, the entire FAULT register is
cleared when either the ON pin or bit D3 goes from high
to low, or if INTV
lockout. Pulling the UVL pin below its 1.21V reset thresh-
old also clears the entire FAULT register. When the UVL
pin is brought back above 1.21V but below 2.291V, the
undervoltage fault bit B1 is set if the UVH pin is below
2.56V. This can be avoided by holding the UVH pin above
2.56V while toggling the UVL pin to reset faults. Finally,
when EN is brought from high to low, all fault bits except
bit B4 are cleared. The bit B4 that indicates an EN change
of state will be set.
Fault bits with associated conditions that are still pres-
ent (as indicated in the STATUS Register A) cannot be
cleared. The FAULT register will not be cleared when
auto-retrying. When auto-retry is disabled, the existence
of B0 (overvoltage), B1 (undervoltage), B2 (overcurrent)
or B3 (power bad) fault keeps the FET off. After the fault
bit is cleared and a delay of t
(for B4) expires, the FET will turn on again. Note that if
the overvoltage fault bit B0 is cleared by writing a zero
through I
lay. If auto-retry is enabled, then a high value in A0, A1,
A2 or A3 will hold the FET off and the FAULT register is
ignored. Subsequently, when the A0, A1, A2 and A3 bits
are cleared, the FET is allowed to turn on again.
20
2
C, the FET is allowed to turn on without a de-
CC
falls below its 4.25V undervoltage
D
(for B0, B1 and B3) or 4t
D
Turning the LTC4261/LTC4261-2 On and Off
Many methods of on/off control are possible using the
ON, EN, UV/OV, FLTIN or PGIO pins along with the I
port. The EN pin works well with logic inputs or fl oat-
ing switch contacts; I
where the board operates only under command of a
central control processor and the ON pin is useful with
signals referenced to RTN, as are the UV (UVH, UVL) and
OV pins. PGIO and FLTIN control nothing directly, but are
useful for I
important signals.
On/off control is possible with or without I
tion. Further, the LTC4261/LTC4261-2 may reside on
either the removable board or on the backplane. Even
when operating autonomously, the I
ercise control over the GATE output, although depending
on how they are connected, EN and ON could subse-
quently override conditions set by I
fault conditions seize control as needed to turn off the
GATE output, regardless of the state of EN, ON or the I
port. Figure 8 shows fi ve confi gurations of on/off control
of the LTC4261/LTC4261-2.
Determining factors in selecting a pin confi guration for
autonomous operation are the polarity and voltage of the
controlling signal.
Optical Isolation. Figure 8a shows an optoisolator driv-
ing the ON pin. Rising and falling edges at the ON pin
turn the GATE output on and off. If ON is already high
when power is applied, GATE is delayed one t
The status of ON can be examined or overridden through
the I
backplane and board resident applications.
Logic Control. Figure 8b shows an application using log-
ic signal control. Again, the ON pin is used as an input;
all remarks made concerning optoisolator control apply
here as well.
2
C port at register bit D3. This circuit works in both
2
C monitoring of connection sense or other
2
C control is intended for systems
2
C. UV, OV and other
2
C port can still ex-
2
C interven-
D
period.
42612fb
2
2
C
C