MIC2591B-2YTQ Micrel Inc, MIC2591B-2YTQ Datasheet - Page 5

• Manufacturer Part Number: MIC2591B-2YTQ
• Description: IC CTRLR HOTPLUG PCI DUAL 48TQFP
• Manufacturer: Micrel Inc
• Type: Hot-Swap Controllerr

Specifications of MIC2591B-2YTQ

• Applications: General Purpose, PCI Express
• Internal Switch(s): No
• Voltage - Supply: 3.3V, 12V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1098

Pin Description (continued)
March 2005
Pin Number
Pin Number
Pin Number
Pin Number
33
33
33
33
26
15
15
15
22
22
22
22
44
44
44
43
43
43
43
45
45
45
45
42
42
42
42
35
35
35
35
31
31
31
31
36
36
36
36
28
28
28
28
11
11
11
2
2
2
2
6
6
6
6
1
1
1
1
9
9
9
9
/FORCE_ONA
/FORCE_ONA
/FORCE_ONA
/FORCE_ONA
/FORCE_ONB
/FORCE_ONB
/FORCE_ONB
/FORCE_ONB
CFILTERA
CFILTERA
CFILTERA
CFILTERA
CFILTERB
CFILTERB
CFILTERB
CFILTERB
/PWRGDA
/PWRGDA
/PWRGDA
/PWRGDA
/PWRGDB
/PWRGDB
/PWRGDB
/PWRGDB
Pin Name
Pin Name
Pin Name
Pin Name
AUXENB
AUXENB
AUXENB
AUXENB
AUXENA
AUXENA
AUXENA
AUXENA
/FAULTB
/FAULTB
/FAULTB
/FAULTB
VSTBYB
/FAULTA
/FAULTA
/FAULTA
/FAULTA
VSTBYA
VSTBYA
VSTBYA
VAUXB
VAUXB
VAUXB
VAUXB
VAUXA
VAUXA
VAUXA
IREF
IREF
IREF
IREF
ONA
ONA
ONA
ONB
ONB
ONB
ONB
Pin Function
Pin Function
Pin Function
Pin Function
A resistor connected between this pin and GND sets the ADC current
A resistor connected between this pin and GND sets the ADC current
A resistor connected between this pin and GND sets the ADC current
A resistor connected between this pin and GND sets the ADC current
measurement gain for the VAUX[A/B] outputs. This resistor must be
measurement gain for the VAUX[A/B] outputs. This resistor must be
measurement gain for the VAUX[A/B] outputs. This resistor must be
measurement gain for the VAUX[A/B] outputs. This resistor must be
23.2kΩ±1%.
23.2kΩ±1%.
23.2kΩ±1%.
23.2kΩ±1%.
Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
to ensure that the chip is accessible during standby modes. A UVLO circuit
to ensure that the chip is accessible during standby modes. A UVLO circuit
to ensure that the chip is accessible during standby modes. A UVLO circuit
to ensure that the chip is accessible during standby modes. A UVLO circuit
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
threshold. Both pins must be connected together at the MIC2591B controller.
3.3VAUX Outputs to PCI Express Card Slots: These outputs connect
3.3VAUX Outputs to PCI Express Card Slots: These outputs connect
3.3VAUX Outputs to PCI Express Card Slots: These outputs connect
the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
400mΩ MOSFETs. These outputs are current limited and protected against
short-circuit faults.
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
these controls only after the V
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
these pins to GND if using SMI power control. Also, see pin description for
/FAULTA and /FAULTB.
Enable Inputs: Rising-edge triggered. Used to enable or disable the
Enable Inputs: Rising-edge triggered. Used to enable or disable the
Enable Inputs: Rising-edge triggered. Used to enable or disable the
Enable Inputs: Rising-edge triggered. Used to enable or disable the
VAUX[A/B] outputs. The outputs can be switched on by these controls only
VAUX[A/B] outputs.
VAUX[A/B] outputs.
VAUX[A/B] outputs.
after the V
Electrical Characteristics Table).Taking AUXEN[A/B] low after a fault resets
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
SMI power control. Also, see pin description for /FAULTA and /FAULTB.
Overcurrent Timers: Capacitors connected between these
Overcurrent Timers: Capacitors connected between these
Overcurrent Timers: Capacitors connected between these
Overcurrent Timers: Capacitors connected between these
pins and GND set the duration of t
pins and GND set the duration of t
pins and GND set the duration of t
pins and GND set the duration of t
delay (t
delay (t
delay (t
delay (t
before its circuit breaker is tripped.
before its circuit breaker is tripped.
before its circuit breaker is tripped.
before its circuit breaker is tripped.
Power-is-Good Outputs: Open-drain, active-low. Asserted when a slot has
Power-is-Good Outputs: Open-drain, active-low. Asserted when a slot has
Power-is-Good Outputs: Open-drain, active-low. Asserted when a slot has
Power-is-Good Outputs: Open-drain, active-low. Asserted when a slot has
been commanded to turn on and has successfully begun delivering power
been commanded to turn on and has successfully begun delivering power
been commanded to turn on and has successfully begun delivering power
been commanded to turn on and has successfully begun delivering power
to its respective +12V, +3.3V, and VAUX outputs. Each pin requires an
external pull-up resistor to V
Fault Outputs: Open-drain, active-low. Asserted whenever the
Fault Outputs: Open-drain, active-low. Asserted whenever the
Fault Outputs: Open-drain, active-low. Asserted whenever the
Fault Outputs: Open-drain, active-low. Asserted whenever the
circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to V
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
was asserted in response to a fault condition on one of the slot’s MAIN out-
puts (+12V or +3.3V).
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] was asserted in response to a fault condition on the slot’s VAUX
output. If a fault condition occurred on both the MAIN and VAUX outputs of
the same slot, then both ON[A/B] and AUXEN[A/B] must be brought low to
deassert the /FAULT[A/B] output.
Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
VAUX), while specifi cally defeating all protections on those supplies. This
explcitly includes all overcurrent and short circuit protections, and on-chip
thermal protection for the VAUX[A/B] supplies. Additionally included are the
UVLO protections for the +3.3V and +12V main supplies. The
/FORCE_ON[A/B] pins do not disable UVLO protection for the VAUX[A/B]
supplies. These input pins are intended for diagnostic purposes only.
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
register set will continue to refl ect the actual state of each slot’s supplies.
There is a pair of register bits, accessible via the SMBus, which can be set
There is a pair of register bits, accessible via the SMBus, which can be set
There is a pair of register bits, accessible via the SMBus, which can be set
There is a pair of register bits, accessible via the SMBus, which can be set
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
pins -- See CNTRL[A/B] Register Bit D[2].
3.3V Standby Input Voltage: Required to support PCI Express VAUX
3.3V Standby Input Voltage: Required to support PCI Express VAUX
3.3V Standby Input Voltage: Required to support PCI Express VAUX
output(s). These inputs are the primary supply for the MIC2591B and must
output(s). These inputs are the primary supply for the MIC2591B and must
be applied at all times for the controller to function properly.
be applied at all times for the controller to function properly.
be applied at all times for the controller to function properly.
be applied at all times for the controller to function properly.
FLT
STBY
STBY
STBY
) is the amount of time for which a slot remains in current limit
5
input supply is valid and stabe (i.e., t
input supply is valid and stabe (i.e., t
STBY
STBY
STBY
STBY
STBY
STBY
.
.
FLT
input supply is valid and stabe (i.e., t
input supply is valid and stabe (i.e., t
for each slot. The overcurrent fi lter
POR
elapses - See the
M9999-033105
STBY
STBY
STBY
POR
.
.