PCA9512AD,112 NXP Semiconductors, PCA9512AD,112 Datasheet - Page 5

• Manufacturer Part Number: PCA9512AD,112
• Description: IC LEVSHIFT I2C/SMBUS BUFF 8SOIC
• Manufacturer: NXP Semiconductors
• Type: I²C-Bus and SMBus Switchr

Specifications of PCA9512AD,112

• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Applications: Hot-Swap/SMB Buffer
• Internal Switch(s): Yes
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Logic Family: PCA
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 3 / 3
• Logic Type: Bus Buffer
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3361-5; 935279721112; PCA9512AD

NXP Semiconductors
PCA9512A_PCA9512B
Product data sheet
8.2 Connect circuitry
8.3 Maximum number of devices in series
bus idle’ detect circuit is enabled. When all the SDAn and SCLn pins have been HIGH for
the bus idle time or when all pins are HIGH and a STOP condition is seen on the SDAIN
and SCLIN pins, the connect circuitry is activated, connecting SDAIN to SDAOUT and
SCLIN to SCLOUT. The 1 V precharge circuitry is disabled when the connection is made,
unless the ACC pin is LOW; the rise time accelerators are enabled at this time also.
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as
SCLIN and SCLOUT become identical, with each acting as a bidirectional buffer that
isolates the input bus capacitance from the output bus capacitance while communicating.
If V
forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the
PCA9512A/B. The same is also true for the SCLn pins. Noise between 0.7V
on the SDAIN and SCLIN pins, and 0.7V
is generally ignored because a falling edge is only recognized when it falls below 0.7V
for SDAIN and SCLIN (or 0.7V
least 1.25 V/μs. When a falling edge is seen on one pin, the other pin in the pair turns on a
pull-down driver that is referenced to a small voltage above the falling pin. The driver will
pull the pin down at a slew rate determined by the driver and the load. The first falling pin
may have a fast or slow slew rate; if it is faster than the pull-down slew rate, then the initial
pull-down rate will continue until it is LOW. If the first falling pin has a slow slew rate, then
the second pin will be pulled down at its initial slew rate only until it is just above the first
pin voltage then they will both continue down at the slew rate of the first.
Once both sides are LOW they will remain LOW until all the external drivers have stopped
driving LOWs. If both sides are being driven LOW to the same (or nearly the same) value
by external drivers, which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving, that pin will rise and rise above
the nominal offset voltage until the internal driver catches up and pulls it back down to the
offset voltage. This bounce is worst for low capacitances and low resistances, and may
become excessive. When the last external driver stops driving a LOW, that pin will bounce
up and settle out just above the other pin as both rise together with a slew rate determined
by the internal slew rate control and the RC time constant. As long as the slew rate is at
least 1.25 V/μs, when the pin voltage exceeds 0.6 V, the rise time accelerator circuits are
turned on and the pull-down driver is turned off. If the ACC pin is LOW, the rise time
accelerator circuits will be disabled, but the pull-down driver will still turn off.
Each buffer adds about 0.1 V dynamic level offset at 25 °C with the offset larger at higher
temperatures. Maximum offset (V
level at the signal origination end (master) is dependent upon the load and the only
specification point is the I
lightly loaded the V
after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the
rising edge accelerator (about 0.6 V). With great care a system with four buffers may
work, but as the V
the rising edge accelerator thus introducing false clock edges. Generally it is
recommended to limit the number of buffers in series to two, and to keep the load light to
minimize the offset.
CC
≠ V
CC2
, then a level shifting function is performed between input and output. A LOW
All information provided in this document is subject to legal disclaimers.
OL
OL
moves up from 0.1 V, noise or bounces on the line will result in firing
may be ~0.1 V. Assuming V
Rev. 5 — 5 January 2011
2
Level shifting hot swappable I
C-bus specification of 3 mA will produce V
CC2
offset
for SDAOUT and SCLOUT pins) with a slew rate of at
) is 0.150 V with a 10 kΩ pull-up resistor. The LOW
CC2
PCA9512A; PCA9512B
and V
OL
CC2
= 0.1 V and V
on the SDAOUT and SCLOUT pins
2
C-bus and SMBus bus buffer
offset
OL
< 0.4 V, although if
© NXP B.V. 2011. All rights reserved.
= 0.1 V, the level
CC
and V
5 of 24
CC
CC