LT4220CGN#PBF Linear Technology, LT4220CGN#PBF Datasheet - Page 7

• Manufacturer Part Number: LT4220CGN#PBF
• Description: IC CNTRLR DUAL HOT SWAP 16-SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LT4220CGN#PBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.7 V ~ 16.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Output Voltage: 8V
• Internal Switch: No
• Supply Voltage Range: ± 2.7V To ± 16.5V
• Digital Ic Case Style: SSOP
• No. Of Pins: 16
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PI FU CTIO S
V
ranges from –2.7V to –16.5V for normal operation. I
typically –1.6mA. An internal undervoltage lockout circuit
disables the device for inputs greater than –2.45V. A 10 ,
1 F RC bypass network from V
transients from the device.
SENSEK (Pin 2): Negative Supply Current Limit Kelvin
Sense Pin. Connect to V
SENSE
A sense resistor is placed in the supply path between
SENSEK and SENSE
the voltage across the sense resistor to
–50mV (SENSEK – SENSE
than –0.7V. If V
the sense resistor decreases linearly and stops at –15mV
when V
SENSEK.
GATE
N-Channel FET. An internal 10 A current source drives the
pin. An external capacitor connected from the GATE
to V
The voltage is clamped to 9V above V
When the current limit is reached, the GATE
will be adjusted to maintain a constant voltage across the
R
the TIMER pin voltage exceeds 1.24V, the fault latch will be
set and both GATE
The GATE
below 1.24V, the ON
is in the undervoltage lockout voltage range, or the fault
latch is set by the TIMER pin rising above 1.24V.
FB
pin monitors the negative output voltage (V
external resistive divider. When the voltage on FB
below –1.24V and the initial GATE
reached a maximum (indicated by setting the internal
GATE
the PWRGD pin is released. PWRGD is pulled low when the
FB
ORed with the FB
EE
S
–
–
–
U
OUT
(Pin 5): Negative Power Good Comparator Input. This
(Pin 1): Negative Supply. The negative supply input
pin is above –1.185V. Note the PWRGD pin is wire-
resistor while the timer capacitor starts to charge. If
–
–
(Pin 4): Gate Drive for the External Negative Supply
good latch) and the FB
–
FB –
–
(Pin 3): Negative Supply Current Limit Sense Pin.
will control the rising slope of the V
–
U
is 0V. If current limit is not used, connect to
pin is pulled to V
FB –
+
–
pin conditions.
goes above –0.7V, the voltage across
–
–
U
and GATE
. The current limit circuit will regulate
pin is above –1.24V, or either supply
IN
–
–
.
) when the FB
+
EE
IN
+
release conditions are met,
–
pins will be pulled low.
whenever the ON
to the V
–
EE
drive voltage has
.
EE
–
voltage is less
pin decouples
OUT
–
OUT
pin voltage
–
) with an
–
+
signal.
pin is
–
EE
–
pin
is
is
FB
amplifier input offset to provide foldback current limit. The
FB
fier offset from –52mV to –15mV for FB
–0.75V < FB
current limit, the FB
range: –1.3V > FB
negative then –5.8V for normal operation.
ON
This pin monitors the negative input voltage (V
external resistive divider for undervoltage lockout. When
the voltage at the ON
threshold (–1.24V), the negative supply is considered
good. If the ON
GATE
should be set to –1.3V > ON
TRACK (Pin 7): Supply Tracking Mode Control. If the TRACK
pin is pulled high, the internal supply tracking circuit will
be enabled during start-up. The TRACK circuit monitors
the FB
small voltage range by controlling the GATE
charge currents. The tracking is disabled when either FB
comparator indicates the output is good. Tracking is re-
enabled if ON
–1.185V or either supply is below the internal undervoltage
lockout. Typically, the TRACK pin is tied to GND or to V
If left floating, tracking is enabled.
TIMER (Pin 8): Fault Time Out Control. An external timing
capacitor at this pin programs the maximum time the part
is allowed to remain in current limit before issuing a fault
and turning off the external FETs. Additionally, for
autorestart, this pin controls the time before an autorestart
is initiated.
When the part goes into current limit, a 65 A pull-up
current source starts to charge the timing capacitor. When
the voltage reaches V
latch is set, FAULT pulls low and both GATE pins are pulled
low; the pull-up current will be turned off and the capacitor
is discharged by a 3.3 A pull-down current. When the
TIMER pin falls below 0.5V, the part is allowed to restart
if the ON
internal fault latch—typically done by connecting the
–
–
–
pin linearly reduces the negative supply sense ampli-
also controls the negative supply current limit sense
(Pin 6): The Negative Supply Good Comparator Input.
+
+
are pulled low. If ON
and the FB
+
pin is pulsed below 1.185V, thereby resetting
–
+
< 0V. To disable V
is pulled below 1.185V, ON
–
pin rises above –1.185V, both GATE
–
–
> V
–
pins to keep their magnitude within a
–
pin should be set to a voltage in the
pin is below the V
EE
TIMERH
+ 0.5V but should never be more
–
–
> V
(1.24V), the internal fault
is not used, the ON
EE
EE
PWRGD and foldback
+ 0.5V.
ON
–
–
–
is pulled above
LT4220
H
in the range
+
high-to-low
and GATE
EE
) with an
–
–
7
and
4220f
pin
CC
–
.