ADE7753ARS Analog Devices Inc, ADE7753ARS Datasheet - Page 26

• Manufacturer Part Number: ADE7753ARS
• Description: IC ENERGY METERING DETEC 20-SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7753ARS

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7753ZEB - BOARD EVALUATION AD7753

ADE7753
PHASE COMPENSATION
When the HPF is disabled, the phase error between Channel 1
and Channel 2 is 0 from dc to 3.5 kHz. When HPF is enabled,
Channel 1 has the phase response illustrated in Figure 58 and
Figure 59. Also shown in Figure 60 is the magnitude response of
the filter. As can be seen from the plots, the phase response is
almost 0 from 45 Hz to 1 kHz. This is all that is required in
typical energy measurement applications. However, despite
being internally phase compensated, the ADE7753 must work
with transducers, which could have inherent phase errors. For
example, a phase error of 0.1° to 0.3° is not uncommon for a
current transformer (CT). These phase errors can vary from
part to part, and they must be corrected in order to perform
accurate power calculations. The errors associated with phase
mismatch are particularly noticeable at low power factors. The
ADE7753 provides a means of digitally calibrating these small
phase errors. The ADE7753 allows a small time delay or time
advance to be introduced into the signal processing chain to
compensate for small phase errors. Because the compensation is
in time, this technique should be used only for small phase
errors in the range of 0.1° to 0.5°. Correcting large phase errors
using a time shift technique can introduce significant phase
errors at higher harmonics.
The phase calibration register (PHCAL[5:0]) is a twos comple-
ment signed single-byte register that has values ranging from
0x21 (–31d) to 0x1F (31d).
The register is centered at 0x0D, so that writing 0x0D to the
register gives 0 delay. By changing the PHCAL register, the time
delay in the Channel 2 signal path can change from –102.12 µs
to +39.96 µs (CLKIN = 3.579545 MHz). One LSB is equivalent
to 2.22 µs (CLKIN/8) time delay or advance. A line frequency of
60 Hz gives a phase resolution of 0.048° at the fundamental (i.e.,
360° × 2.22 µs × 60 Hz). Figure 57 illustrates how the phase
compensation is used to remove a 0.1° phase lead in Channel 1
due to the external transducer. To cancel the lead (0.1°) in
Channel 1, a phase lead must also be introduced into Channel 2.
The resolution of the phase adjustment allows the introduction
of a phase lead in increment of 0.048°. The phase lead is achieved
by introducing a time advance into Channel 2. A time advance
of 4.48 µs is made by writing −2 (0x0B) to the time delay block,
thus reducing the amount of time delay by 4.48 µs, or equiva-
lently, a phase lead of approximately 0.1° at line frequency of
60 Hz. 0x0B represents –2 because the register is centered with 0
at 0x0D.
Rev. A | Page 26 of 60
V 1
V 2
V1P
V1N
V2P
V2N
V1
–0.1
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
PGA1
PGA2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
V2
Figure 58. Combined Phase Response of the HPF and
Figure 59. Combined Phase Response of the HPF and
40
60Hz
Phase Compensation (10 Hz to 1 kHz)
Phase Compensation (40 Hz to 70 Hz)
ADC 2
0.1°
ADC 1
45
Figure 57. Phase Calibration
10
2
1
50
FREQUENCY (Hz)
FREQUENCY (Hz)
--100µs TO +34µs
5
DELAY BLOCK
0
PHCAL [5:0]
4.48µs/LSB
0
1
55
HPF
0
1
1
0
10
24
60
3
CHANNEL 2 DELAY
REDUCED BY 4.48µs
(0.1°LEAD AT 60Hz)
0Bh IN PHCAL [5.0]
V2
65
24
02875-0-057
V1
60Hz
02875-0-058
LPF2
10
02875-0-056
70
4