ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 80

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7878
Bit
Location
6
7
8
9
10
11
12
13
14
15
16
17
18
31:19
Table 34. MASK1 Register (Address 0xE50B)
Bit
Location
0
1
2
3
4
5
6
Bit Name
REVAPA
REVAPB
REVAPC
REVPSUM1
REVRPA
REVRPB
REVRPC
REVPSUM2
CF1
CF2
CF3
DREADY
REVPSUM3
Reserved
Bit Name
NLOAD
FNLOAD
VANLOAD
ZXTOVA
ZXTOVB
ZXTOVC
ZXTOIA
0
0
0
0
0
0
Default Value
0
Default Value
0
0
0
0
0
0
0
0
0
0
00 0000 0000
0000
Description
When this bit is set to 1, it enables an interrupt when at least one phase enters no load condition
based on total active and reactive powers.
When this bit is set to 1, it enables an interrupt when at least one phase enters no load condition
based on fundamental active and reactive powers.
When this bit is set to 1, it enables an interrupt when at least one phase enters no load condition
based on apparent power.
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase A voltage is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase B voltage is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase C voltage is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase A current is
missing.
Description
When this bit is set to 1, it enables an interrupt when the Phase A active power identified by Bit 6
(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the Phase B active power identified by Bit 6
(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the Phase C active power identified by Bit 6
(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1
datapath changes sign.
When this bit is set to 1, it enables an interrupt when the Phase A reactive power identified by Bit
7 (REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the Phase B reactive power identified by
Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the Phase C reactive power identified by
Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2
datapath changes sign.
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at the CF1
pin, that is an active low pulse is generated. The interrupt can be enabled even if the CF1 output
is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE[15:0] register. The type of power used at
the CF1 pin is determined by Bits[2:0] (CF1SEL) in the CFMODE[15:0] register (see Table 39).
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at CF2 pin,
that is an active low pulse is generated. The interrupt may be enabled even if the CF2 output is
disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE[15:0] register. The type of power used at
the CF2 pin is determined by Bits[5:3] (CF2SEL) in the CFMODE[15:0] register (see Table 39).
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3 pin,
that is an active low pulse is generated. The interrupt may be enabled even if the CF3 output is
disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE[15:0] register. The type of power used at
the CF3 pin is determined by Bits[8:6] (CF3SEL) in the CFMODE[15:0] register (see Table 39).
When this bit is set to 1, it enables an interrupt when all periodic (at 8 kHz rate) DSP
computations finish.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3
datapath changes sign.
Reserved. These bits do not manage any functionality.
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