ADE7763ARSZRL Analog Devices Inc, ADE7763ARSZRL Datasheet - Page 5
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ADE7763ARSZRL
Manufacturer Part Number
ADE7763ARSZRL
Description
IC ENERGY METERING 1PHASE 20SSOP
Manufacturer
Analog Devices Inc
Datasheet
1.ADE7763ARSZRL.pdf
(56 pages)
Specifications of ADE7763ARSZRL
Input Impedance
390 KOhm
Measurement Error
0.1%
Voltage - I/o High
2.4V
Voltage - I/o Low
0.8V
Current - Supply
3mA
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SSOP (0.200", 5.30mm Width)
Meter Type
Single Phase
Ic Function
Single-Phase Active And Apparent Energy Metering IC
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
SSOP
No. Of Pins
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADE7763ZEB - BOARD EVALUATION FOR ADE7763
Lead Free Status / Rohs Status
Compliant
Other names
ADE7763ARSZRL
ADE7763ARSZRLTR
ADE7763ARSZRLTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADE7763ARSZRL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
TIMING CHARACTERISTICS
AV
Table 2. Timing Characteristics
Parameter
Write Timing
Read Timing
1
2
3
4
5
Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.
See Figure 3, Figure 4, and the Serial Interface section.
Minimum time between read command and data read for all registers except waveform register, which is t
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
t
t
t
t
t
t
t
t
t
t
t
t
t
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
3
4
5
= DV
SCLK
DOUT
SCLK
DIN
DIN
CS
CS
DD
= 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, T
t
t
1
1
1
0
Spec
50
50
50
10
5
400
50
100
4
50
30
100
10
100
10
0
0
t
2
A5
A5
1, 2
t
3
COMMAND BYTE
COMMAND BYTE
A4
A4
t
4
A3
A3
t
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min)
μs min
ns min
ns min
ns max
ns min
ns max
ns min
A2
A2
A1
A1
Figure 3. Serial Write Timing
Figure 4. Serial Read Timing
A0
A0
Rev. B | Page 5 of 56
t
t
7
t
9
11
Test Conditions/Comments
CS falling edge to first SCLK falling edge.
SCLK logic high pulse width.
SCLK logic low pulse width.
Valid data setup time before falling edge of SCLK.
Data hold time after SCLK falling edge.
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS hold time after SCLK falling edge.
Minimum time between read command (i.e., a write to communication
register) and data read.
Minimum time between data byte transfers during a multibyte read.
Data access time after SCLK rising edge following a write to the
communication register.
Bus relinquish time after falling edge of SCLK.
Bus relinquish time after rising edge of CS .
DB7
DB7
MOST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE
9
= 500 ns min.
t
11
DB0
DB0
t
t
7
10
MIN
LEAST SIGNIFICANT BYTE
DB7
LEAST SIGNIFICANT BYTE
DB7
to T
t
6
MAX
= −40°C to +85°C.
t
12
DB0
DB0
t
13
t
ADE7763
8