MCP3909-I/SS Microchip Technology, MCP3909-I/SS Datasheet - Page 25

• Manufacturer Part Number: MCP3909-I/SS
• Description: IC POWER METERING-1 PHASE 24SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3909-I/SS

• Package / Case: 24-SSOP (0.200", 5.30mm Width)
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.85V
• Current - Supply: 2.3mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Meter Type: Single Phase
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Supply Voltage Range: 4.5V To 5.5V
• Digital Ic Case Style: SSOP
• No. Of Pins: 24
• Interface Type: Serial, SPI
• Supply Voltage Max: 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP3909EV-MCU16 - EVALUATION BOARD FOR MCP3909MCP3909RD-3PH1 - REF DESIGN MCP3909 3PH ENGY MTR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.4
This mode allows the user to retrieve the individual
channel information from the ADC outputs. The ADC
outputs of both channels are synchronized together
and their data ready is represented by the data ready
pulse on SDO. If the ADC output values are not clocked
out of the device, they will be over-written. A 32-bit data
word is given, each channel is 16 bits (15 bits + sign),
presented in 2's complement coding. Channel 1 comes
first then channel 0.
FIGURE 5-5:
© 2006 Microchip Technology Inc.
TABLE 5-3:
0 111 1111 1111 1111
0 111 1111 1111 1110
0 000 0000 0000 0000
1 111 1111 1111 1111
1 000 0000 0000 0001
1 000 0000 0000 0000
NEG / SDO
F2 / SCK
F1 / SDI
F0 / CS
Dual Channel Output Mode
Binary
CODING
CHANNEL OUTPUT MODE
Hi-z
Dual Channel Output Mode.
Channel 0 Code
DR
Channel 1 Code
+ 32,767
+ 32,766
-1
- 32,767
- 32,768
0
Decimal
=
1
D31
⎛
⎜
⎝
Channel 1
(
------------------------------------
V
2
D30
=
X 16
X 16
IN+
(
------------------------------------
V
V IN+ V IN-
15
REF
D17
–
V
V
REF
16
IN-
D16
–
X 32
)
X 32
Hi-z
⎞
⎟
⎠
×
)
32768
A data ready flag (DR) is output for every MCLK / 256
clock cycles and a new filter output value is ready. If the
dual channel output values are not clocked, and is not
clocked out of the device, they will be over-written.
The following formulas relate the channel input
voltages to their respective output code. The code
locks to +32767 on the positive side, and to -32768 on
the negative side.
5.5
There are two options for the channel output data. The
first options collects the channel data pre-high pass fil-
ter, or the output of the SINC filter of the delta sigma
modulator. The second option collects the channel data
post high pass filter. It is important to note that the HPF
pin controls the state of the high pass filter for this sec-
ond option. If the HPF pin is low, the post high pass fil-
ter mode will output all zero's. This HPF pin must be
high to access the post HPF data in the channel output
mode.
×
32768
17 18
D15 D14 D1
Channel 0
×
⎛
⎝
×
X 16
X 16
High-Pass Filter Control
8.06
⎛
⎝
31 32
8.06
×
0.66
---------- -
0.47
×
0.47
---------- -
0.66
D0
⎞
⎠
×
⎞
⎠
PGA
MCP3909
Hi-z
DS22025A-page 25