ADE7758ARWZ Analog Devices Inc, ADE7758ARWZ Datasheet - Page 67

• Manufacturer Part Number: ADE7758ARWZ
• Description: IC ENERGY METERING 3PHASE 24SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7758ARWZ

• Input Impedance: 380 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 8mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• Ic Function: Poly Phase Multifunction Energy Metering IC
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SOIC
• No. Of Pins: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LINE CYCLE ACCUMULATION MODE REGISTER (0x17)
The functionalities involved the line-cycle accumulation mode in the ADE7758 are defined by writing to the LCYCMODE register.
Table 22 summarizes the functionality of each bit in the LCYCMODE register.
Table 22. LCYCMODE Register
Bit
Location
0
1
2
3 to 5
6
7
Bit
Mnemonic
LWATT
LVAR
LVA
ZXSEL
RSTREAD
FREQSEL
Default
Value
0
0
0
7
1
0
Description
Setting this bit places the watt-hour accumulation registers (AWATTHR, BWATTHR, and CWATTHR
registers) into line-cycle accumulation mode.
Setting this bit places the VAR-hour accumulation registers (AVARHR, BVARHR, and CVARHR registers)
into line-cycle accumulation mode.
Setting this bit places the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR registers) into
line-cycle accumulation mode.
These bits select the phases used for counting the number of zero crossings in the line-cycle
accumulation mode. Bit 3, Bit 4, and Bit 5 select Phase A, Phase B, and Phase C, respectively. More than
one phase can be selected for the zero-crossing detection, and the accumulation time is shortened
accordingly.
Setting this bit enables the read-with-reset for all the WATTHR, VARHR, and VAHR registers for all three
phases, that is, a read to those registers resets the registers to 0 after the content of the registers have
been read. This bit should be set to Logic 0 when the LWATT, LVAR, or LVA bits are set to Logic 1.
Setting this bit causes the FREQ (0x10) register to display the period, instead of the frequency of the
line input.
Rev. D | Page 67 of 72
ADE7758