PCF8579T/1,118 NXP Semiconductors, PCF8579T/1,118 Datasheet
![IC LCD DRIVER COLUMN 56-VSOP](/photos/7/35/73530/568-56-vsop_sot190-1_sml.jpg)
PCF8579T/1,118
Specifications of PCF8579T/1,118
PCF8579TD-T
PCF8579TD-T
Related parts for PCF8579T/1,118
PCF8579T/1,118 Summary of contents
Page 1
PCF8579 LCD column driver for dot matrix graphic displays Rev. 05 — 11 May 2009 1. General description The PCF8579 is a low power CMOS graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has 40 ...
Page 2
... NXP Semiconductors 3. Applications I Automotive information systems I Telecommunication systems I Point-of-sale terminals I Industrial computer terminals I Instrumentation 4. Ordering information Table 1. Type number PCF8579T/1 PCF8579H/1 PCF8579HT/1 [1] Should not be used for new designs. 5. Marking Table 2. Type number PCF8579T/1 PCF8579H/1 PCF8579HT/1 PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays ...
Page 3
... NXP Semiconductors 6. Block diagram LCD TEST V SS POWER-ON RESET SCL INPUT FILTERS SDA n.c. (1) Operates at LCD voltage levels, all other blocks operate at logic levels. Fig 1. Block diagram PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays C39 - C0 COLUMN ...
Page 4
... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays 1 SDA SCL 2 SYNC 3 4 CLK TEST 6 SA0 n. LCD C39 17 18 C38 19 C37 C36 20 C35 21 22 C34 C33 23 C32 24 C31 25 26 C30 C29 ...
Page 5
... NXP Semiconductors Fig 3. PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays SDA 7 SCL 8 SYNC 9 10 CLK TEST 12 13 SA0 Top view. For mechanical details, see Figure Pinning diagram of PCF8579H/1 (LQFP64) Rev. 05 — 11 May 2009 PCF8579 48 47 ...
Page 6
... NXP Semiconductors Fig 4. PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays SDA 7 SCL 8 SYNC 9 10 CLK TEST 12 13 SA0 Top view. For mechanical details, see Figure Pinning diagram of PCF8579HT/1 (TQFP64) Rev. 05 — 11 May 2009 PCF8579 48 47 ...
Page 7
... NXP Semiconductors 7.2 Pin description Table 3. Symbol SDA SCL SYNC CLK V SS [1] TEST SA0 [2] n. LCD C39 to C0 [1] The TEST pin must be connected to V [2] Do not connect, these pins are reserved. 8. Functional description The PCF8579 column driver is designed for use with the PCF8578. Together they form a general purpose LCD dot matrix chip set ...
Page 8
... NXP Semiconductors Remark: Do not transfer data on the I reset action to complete. 8.2 Multiplexed LCD bias generation The bias levels required to produce maximum contrast depend on the multiplex rate and the LCD threshold voltage (V LCD exhibits 10 % contrast. the discrimination ratios (D) for the different multiplex rates as functions of V ...
Page 9
... NXP Semiconductors Table 5. Discrimination ratios V off RMS ------------------------ - V oper V on RMS ----------------------- V oper V on RMS D = ------------------------ - V off RMS V oper ------------- - V th Figure 5 Fig 5. PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays Discrimination ratios Multiplex rate 1:8 1:16 0.297 0.245 0.430 ...
Page 10
... NXP Semiconductors 8.3 LCD drive mode waveforms ROW LCD COLUMN LCD SYNC ROW LCD COLUMN LCD SYNC ROW LCD COLUMN LCD SYNC ROW LCD COLUMN LCD SYNC Fig 6. LCD row and column waveforms PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays ...
Page 11
... NXP Semiconductors ROW 1 R1 (t) ROW 2 R2 (t) COL 1 C1 (t) COL 2 C2 (t) V 0.261 V (t) V state 0.261 0.478 V 0.261 V ( state 2 0.261 V 0.478 (t) = C1(t) R1(t). state1 – on RMS = + ---------------------- - -- - ----------------------- - oper V (t) = C2(t) R2(t). state2 – off RMS ------------------------------ - ----------------------- - = oper Fig 7. LCD drive mode waveforms for 1:8 multiplex rate ...
Page 12
... NXP Semiconductors ROW ( LCD ROW ( LCD COL ( LCD COL ( LCD V oper 0.2 V oper ( state 1 0.2 V oper V oper V oper 0.6 V oper 0.2 V oper (t) V state 0.2 V oper 0.6 V oper V oper V (t) = C1(t) R1(t). state1 RMS ---------------------- - = ----- - + ------------------------------ oper V (t) = C2(t) R2(t). state2 – off RMS ...
Page 13
... NXP Semiconductors 8.4 Timing generator The timing generator of the PCF8579 organizes the internal data flow from the RAM to the display drivers. An external synchronization pulse SYNC is received from the PCF8578. This signal maintains the correct timing relationship between cascaded devices. 8.5 Column drivers Outputs C0 to C39 are column drivers which must be connected to the LCD ...
Page 14
... NXP Semiconductors Fig 9. SDA SCL Fig 10. Definition of START and STOP condition SDA SCL MASTER TRANSMITTER / RECEIVER Fig 11. System configuration BY TRANSMITTER Fig 12. Acknowledgement on the I PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays SDA SCL data line stable ...
Page 15
... NXP Semiconductors 2 8.6.5 I C-bus controller 2 The I C-bus controller detects the I data bytes. It performs the conversion of the data input (serial-to-parallel) and the data output (parallel-to-serial). The PCF8579 acts Device selection depends on the I the commands transmitted. 8.6.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines ...
Page 16
... NXP Semiconductors In multiple device applications, the hardware subaddress pins of the PCF8579s (A0 to A3) are connected to V more devices share the same slave address, then each device must be allocated a unique hardware subaddress. slave address byte a. Master transmits to slave receiver (write mode) slave address ...
Page 17
... NXP Semiconductors 8.7 Display RAM The PCF8579 contains divided into 4 banks of 40 bytes (4 transferred to or from the RAM via the I 8.7.1 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows an individual data byte or a series of data bytes to be written into, or read from, the display RAM, controlled by commands sent on the I 8 ...
Page 18
... NXP Semiconductors Table 8. Bit Table 9. Bit [1] Useful for scrolling, pseudo-motion and background preparation of new display content. Table 10. Bit [1] Values shown in decimal. PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays Set-mode - command bit description Symbol Value E[1: M[1:0] ...
Page 19
... NXP Semiconductors Table 11. Bit [1] See operation code for set-start-bank in [2] Values shown in decimal. Table 12. Bit [1] Values shown in decimal. PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays RAM-access - command bit description Symbol Value 111 G[1: [2] Y[1: Table Load-X-address - command bit description ...
Page 20
... NXP Semiconductors 8.9 RAM access LSB MSB Fig 15. RAM addressing scheme There are three RAM-access modes: • Character • Half-graphic • Full-graphic These modes are specified by the bits G[1:0] of the RAM-access command. The RAM-access command controls the order in which data is written to or read from the RAM ...
Page 21
DEVICE SELECT: subaddress 12 RAM ACCESS: character mode bank 1 LOAD X-ADDRESS: X-address = slave address DEVICE SELECT ...
Page 22
PCF8578/PCF8579 driver 1 RAM 4 bytes 40-bits 1 byte bytes ...
Page 23
... NXP Semiconductors 8.9.1 Display control The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The number of rows scanned depends on the multiplex rate set by bits M[1:0] of the set-mode command. bank 0 bank 1 bank 2 bank 3 1:32 multiplex rate and start bank = 2. ...
Page 24
... NXP Semiconductors The display status (all dots on or off and normal or inverse video) is set by the bits E[1:0] of the set-mode command. For bank switching, the RAM bank corresponding to the top of the display is set by the bits B[1:0] of the set-start-bank command. This is shown in Figure 18 ...
Page 25
... NXP Semiconductors 10. Static characteristics Table 14. Static characteristics LCD Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD V power-on reset voltage POR Logic V LOW-level input voltage IL V HIGH-level input voltage IH I leakage current L I LOW-level output current ...
Page 26
... NXP Semiconductors 11. Dynamic characteristics Table 15. Dynamic characteristics All timing values are referenced 3 LCD DD DD Symbol Parameter f clock frequency clk t driver propagation delay PD(drv C-bus f SCL clock frequency SCL t spike pulse width w(spike) t bus free time between a STOP BUF and START condition ...
Page 27
... NXP Semiconductors SDA SCL SDA Fig 20. I PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays t t BUF LOW t HD;STA C-bus timing waveforms Rev. 05 — 11 May 2009 PCF8579 HD;DAT t HIGH t SU;STA © NXP B.V. 2009. All rights reserved. ...
Page 28
... NXP Semiconductors 12. Application information Large display configurations of one PCF8578 and PCF8579 can be recognized on the same I address SA0. Table 16. Pins connected to V Cluster PCF8578 - PCF8579 1 2 PCF8579_5 Product data sheet LCD column driver for dot matrix graphic displays 2 C-bus by using the 4-bit hardware subaddress A[3:0] and the I Example of addressing one PCF8578 and 32 PCF8579 are logic 0 ...
Page 29
rows 3 PCF8578 4 unused columns (ROW MODE SA0 LCD V LCD V ...
Page 30
rows rows PCF8578 4 (ROW MODE) unused columns SA0 ...
Page 31
3 rows PCF8578 V 4 (ROW MODE) unused columns SA0 ...
Page 32
SCL DD V SDA LCD R0 R ext(OSC 3 n.c. n.c. PCF8578 R31/C31 Fig 24. Example of single plane wiring, single screen with 1:32 multiplex rate (PCF8578 in row driver mode) ...
Page 33
... NXP Semiconductors 13. Package outline VSO56: plastic very small outline package; 56 leads pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 3.0 mm 3.3 0.25 0.1 2.8 0.012 0.12 inches 0.01 0.13 0.004 0.11 Notes 1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included. ...
Page 34
... NXP Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT314-2 136E10 Fig 26 ...
Page 35
... NXP Semiconductors TQFP64: plastic thin quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.05 1.2 mm 0.25 0.05 0.95 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT357-1 137E10 Fig 27 ...
Page 36
... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
Page 37
... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
Page 38
... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 19. Acronym CMOS LCD LSB MSB MSL PCB POR RC RAM RMS SCL SDA ...
Page 39
... Release date PCF8579_5 20090511 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added package type TQFP64 • ...
Page 40
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 41
... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 Functional description . . . . . . . . . . . . . . . . . . . 7 8.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2 Multiplexed LCD bias generation . . . . . . . . . . . 8 8.3 LCD drive mode waveforms . . . . . . . . . . . . . . 10 8 ...