DS2790G+T&R Maxim Integrated Products, DS2790G+T&R Datasheet - Page 5

• Manufacturer Part Number: DS2790G+T&R
• Description: IC FUEL GAUGE BATT 28-TDFN
• Manufacturer: Maxim Integrated Products

Specifications of DS2790G+T&R

• Function: Fuel, Gas Gauge/Monitor
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS: JTAG INTERFACE
(2.5V ≤ V
Setup Time for STOP
Condition
Spike Pulse Width that can be
Suppressed by Input Filter
Clock Low Time-Out
Cumulative Clock Low Extend
Time for Slave Device
Cumulative Clock Low Extend
Time for Bus Master
SCL, SDA Input Capacitance
JTAG Logic Reference
TCK High Time
TCK Low Time
TCK Low to TDO Output
TMS, TDI Input Setup to TCK
High
TMS, TDI Input Hold after TCK
High
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
PARAMETER
PARAMETER
DD
≤ 5.5V, T
Maximum current assumuing 100% CPU duty cycle.
This value does not include current in SDA, SCL, and P0.0–P0.5.
All Voltages referenced to V
Voltage register can report up to 4.992V, however VIN pin input saturation occurs at 4.75V minimum.
The secondary short circuit delay is measured from the falling transition on V
is measured from the time V
f
The maximum t
This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
C
Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Devices participating in data transfer will timeout when any clock low exceeds the minimum t
detected a timeout condition must reset the communication no later than the maximum t
specified must be adhered to by both devices as it incorporates the cumulative stretch limit for the master (10ms) and slave
device (25ms).
t
exceeds this time, it will release both SDA and SCL and reset the communication interface.
t
the bus master exceeds this time it is possible for the DS2790 to violate t
SCL
LOW:SEXT
LOW:MEXT
B
⎯total capacitance of one bus line in pF.
must meet the minimum clock low time plus the rise/fall times.
is the cumulative time the slave is allowed to extend the clock from the initial START to the STOP. If the DS2790
is the cumulative time the master is allowed to extend the clock cycles within each byte of a communication sequence. If
A
= -20°C to +70°C.)
HD:DAT
has only to be met if the device does not stretch the LOW period (t
SYMBOL
SYMBOL
t
SS
t
DD
t
LOW:MEXT
LOW:SEXT
t
TIMEOUT
.
SU:STO
t
V
t
C
t
DVTH
THDX
reaches V
t
t
t
TLQ
SP
REF
TH
TL
BIN
POR
(Note 10)
TTO_DIS = 0,
(Note 11)
TLS_DIS = 0,
(Note 12)
TTO_DIS = 0,
TLS_DIS = 0
(Note 13)
- 0.5V to the time DC reaches 50% of V
CONDITIONS
CONDITIONS
5 of 41
TIMEOUT
DD
MIN
MIN
0.6
4.0
4.0
1.0
4.0
to the resultant falling transition on DC. The delay
25
without having violated t
0
CP
(4.5V).
LOW
TIMEOUT
V
TYP
TYP
DD
) of the SCL signal.
TIMEOUT
÷ 2
of 35ms. The maximum value
of 25ms. Devices that have
MAX
MAX
1.0
50
35
25
10
60
LOW:SEXT
.
UNITS
UNITS
ms
ms
ms
pF
µs
ns
µs
µs
µs
µs
µs
V