ISL9206ADRTZ-T Intersil, ISL9206ADRTZ-T Datasheet
ISL9206ADRTZ-T
Specifications of ISL9206ADRTZ-T
Related parts for ISL9206ADRTZ-T
ISL9206ADRTZ-T Summary of contents
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... MARKING RANGE (°C) ISL9206ADHZ-T* 206A -25 to +85 ISL9206ADRTZ-T* 06A -25 to +85 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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... Thermal Resistance (Typical) + 0.5V SOT-23 Package (Note 2x3 TDFN Package (Notes Maximum Junction Temperature (Plastic Package +125°C Maximum Storage Temperature Range . . . . . . . . . .-40°C to +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = -25°C to +85° SYMBOL TEST CONDITIONS V During normal operation DD ...
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Electrical Specifications Unless otherwise noted, all parameters are established over the operational supply voltage and temperature range of the device as follows: T limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not ...
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Typical Applications PACK+ XSD PACK- FIGURE 1. TYPICAL APPLICATION WITH THE ISL9206A POWERED BY THE BATTERY PACK+ XSD PACK- FIGURE 2. TYPICAL APPLICATION WITH THE ISL9206A POWERED BY THE XSD BUS Block Diagram VDD XSD VSS 4 ISL9206A R 2 ...
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Theory of Operation The ISL9206A contains all circuitry required to support battery pack authentication based on a challenge-response scheme. It provides a 16-Byte One-Time Programmable Read-Only Memory (OTPROM) space for the storage 96-Bit of secret for the ...
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ASLP bit in DCFG) during OTP ROM programming. OTP ROM The 16-Byte OTP ROM memory is based on EEPROM technology and is incorporated into the ISL9206A for storage of ...
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The flow chart in Figure 6 summarizes the process that the host needs to execute. 32-BIT PSEUDO-RANDOM CHALLENGE WORD FROM HOST 64-BIT SECRET 32-BIT HASH FUNCTION FLEXIHASH+™ ENGINE 64-BIT HASH SEED 8-BIT AUTHENTICATION CODE FIGURE 5. AUTHENTICATION PROCESS ...
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... XSD Host Bus Interface Communication with the host is achieved through XSD, a light-weight subset of Intersil’s ISD single-wire bus interface. XSD is a programmable-rate pseudo-synchronous bidirectional host-initiated instruction-based serial communication interface that allows up to two slave devices to be attached and addressed separately. It includes features to enable quick and reliable communication ...
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HOST OPEN-DRAIN Open-Drain PORT PIN Port Pin TX RX FIGURE 7. THE CIRCUIT MODEL FOR THE XSD SERIAL BUS XSD TABLE 2. HOST TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING PARAMETER SYMBOL Bit Time 0. ...
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OPCODE DESCRIPTION 00 Write Operation 01 Read Operation (normal) 10 Read Operation (with CRC) Read from device register. Append 1-Byte CRC to the end of the last read frame. 11 Sleep Mode Activation Access Instruction Frame The XSD access instruction ...
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TABLE 7. SYMBOLS IN THE BUS TRANSACTION PROTOCOL SYMBOL DESCRIPTION IFG Host inter-frame gap H IFG Device inter-frame gap D TA Host turn-around time H TA Device turn-around time D Passive CRC Support The CRC feature only supports the read ...
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... These registers are used during the battery pack authentication process. Table 10 describes the mapping of the Authentication registers. Bank 3 is reserved for Intersil production testing only and will not be accessible during normal operation. Accessing the Test and Trim Registers when not in test mode will result in a bus error ...
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ADDRESS NAME DESCRIPTION 2-00 SESL Secrets Selection 2-01 CHLG Challenge Code Register 2-05 AUTH Authentication Code Register TABLE 11. DEFAULT CONFIGURATION (DCFG) REGISTER SETTINGS BIT NAME TYPE DEFAULT 7:6 DAB[1: 5:4 SPD[1: eINT RW 1 ...
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ADDRESS 0-0A/0B/0C/0D: AUTHENTICATION SECRET SET #3 (SE3A/B/C/D) These address locations store the optional third set of secrets to be used for hash calculation. Reading and writing to this register can be disabled by setting the SLO[0] bit at OTP ROM ...
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... One way is to use a spare UART (Universal Asynchronous Receiver/Transmitter). A GPIO (General Purpose Input/Output) can be used if no UART is available for the XSD communication. Refer to application note AN1167 available from Intersil for more information regarding how to implement the XSD bus within a microprocessor. Pull-up Resistor Selection ...
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Small Outline Transistor Plastic Packages (SOT23- 0.20 (0.008 0.10 (0.004 WITH PLATING b1 c BASE METAL ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...