ICE3A2565 Infineon Technologies, ICE3A2565 Datasheet - Page 13
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ICE3A2565
Manufacturer Part Number
ICE3A2565
Description
IC OFFLINE CTRLR SMPS CM 8DIP
Manufacturer
Infineon Technologies
Series
CoolSET®F3r
Specifications of ICE3A2565
Package / Case
8-DIP (0.300", 7.62mm)
Output Isolation
Isolated
Frequency Range
92 ~ 108kHz
Voltage - Input
8.5 ~ 22 V
Voltage - Output
650V
Power (watts)
68W
Operating Temperature
-25°C ~ 130°C
Output Voltage
650V
No. Of Outputs
1
Supply Voltage Range
8.5V To 21V
Voltage Regulator Case Style
DIP
No. Of Pins
8
Operating Temperature Range
-40°C To +150°C
Termination
RoHS Compliant
Input Voltage
265VAC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ICE3A2565X
ICE3A2565XK
SP000015075
ICE3A2565XK
SP000015075
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICE3A2565
Manufacturer:
PHILIPS
Quantity:
32
3.4
Figure 9
3.4.1
The oscillator generates a fixed frequency. The switching
frequency of ICE3Axx65x is f
ICE3Bxx65x f
current source and current sink which determine the
frequency are integrated. The charging and discharging
current of the implemented oscillator capacitor are internally
trimmed, in order to achieve a very accurate switching
frequency. The ratio of controlled charge to discharge
current is adjusted to reach a maximum duty cycle limitation
of D
3.4.2
The oscillator clock output provides a set pulse to the PWM-
Latch when initiating the internal CoolMOS™ conduction.
After setting the PWM-Latch can be reset by the PWM
comparator, the Soft Start comparator or the Current-Limit
comparator. In case of resetting, the driver is shut down
immediately.
Version 2.0
Comparator
Comparator
Soft Start
max
Current
Limiting
PWM
Duty Cycle
=0.72.
Oscillator
Clock
max
PWM Section
Oscillator
PWM-Latch FF1
OSC
PWM Section
= 67kHz. A resistor, a capacitor and a
0.72
G8
1
R
S
OSC
FF1
Q
= 100kHz and for
CoolMOS™
Gate Driver
Internal
PWM Section
G9
Gate
&
13
3.4.3
Figure 10
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing the
switch on slope when exceeding the internal CoolMOS™
threshold. This is achieved by a slope control of the rising
edge at the driver’s output (see Figure 11).
Figure 11
Thus the leading switch on spike is minimized. When the
integrated CoolMOS™ is switched off, the falling shape of
the driver is slowed down when reaching 2V to prevent an
overshoot below ground. Furthermore the driver circuit is
designed to eliminate cross conduction of the output stage.
During powerup when VCC is below the undervoltage
lockout threshold V
low to disable power transfer to the seconding side.
Gate Driver
PWM-Latch
(internal) V
5V
Gate Driver
1
Gate
VCC
Gate Driver
Gate Rising Slope
VCCoff
, the output of the Gate Driver is
Functional Description
ca. t = 130ns
CoolSET™-F3
Gate
CoolMOS™
24 Aug 2005
t