ICE3AS02 Infineon Technologies, ICE3AS02 Datasheet - Page 10

• Manufacturer Part Number: ICE3AS02
• Description: IC OFFLINE CTRLR SMPS CM 8DIP
• Manufacturer: Infineon Technologies
• Series: CoolSET®F3r

Specifications of ICE3AS02

• Output Isolation: Isolated
• Frequency Range: 92 ~ 108kHz
• Voltage - Input: 8.5 ~ 22 V
• Voltage - Output: 500V
• Power (watts): 900mW
• Operating Temperature: -25°C ~ 130°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ICE3AS02X; ICE3AS02XK; SP000015084

3.4
Figure 7
3.4.1
The oscillator generates a fixed frequency. The switching
frequency for ICE3AS02/G is f
ICE3BS02/G f
current source and current sink which determine the
frequency are integrated. The charging and discharging
current of the implemented oscillator capacitor are internally
trimmed, in order to achieve a very accurate switching
frequency. The ratio of controlled charge to discharge
current is adjusted to reach a maximum duty cycle limitation
of D
3.4.2
The oscillator clock output provides a set pulse to the PWM-
Latch when initiating the external Power Switch conduction.
After setting the PWM-Latch can be reset by the PWM
comparator, the Soft Start comparator or the Current-Limit
comparator. In case of resetting, the driver is shut down
immediately.
3.4.3
The Gate Driver is a fast totem pole gate drive which is
designed to avoid cross conduction currents and which is
equipped with a zener diode Z1 (see Figure 8) in order to
improve the control of the Gate attached power transistors as
well as to protect them against undesirable gate
overvoltages.
Version 1.2
Comparator
Comparator
Soft Start
max
Current
Limiting
PWM
=0.72.
Oscillator
Cycle
Clock
Duty
max
PWM Section
Oscillator
PWM-Latch FF1
Gate Driver
PWM Section
OSC
= 67kHz. A resistor, a capacitor and a
0.72
G8
1
S
R
OSC
FF1
Q
= 100kHz and for
PWM Section
G9
&
Gate
Driver
Gate
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
10
Figure 8
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing the
switch on slope when exceeding the external Power Switch
threshold. This is achieved by a slope control of the rising
edge at the driver’s output (see Figure 9).
Figure 9
Thus the leading switch on spike is minimized. When the
external Power Switch is switched off, the falling shape of
the driver is slowed down when reaching 2V to prevent an
overshoot below ground. Furthermore the driver circuit is
designed to eliminate cross conduction of the output stage.
During powerup when VCC is below the undervoltage
lockout threshold V
low to disable power transfer to the secondary side.
PWM-Latch
5V
V
Gate
Gate Driver
Gate Rising Slope
ca. t = 130ns
1
VCCoff
, the output of the Gate Driver is
VCC
Functional Description
Z1
C
Load
= 1nF
02 Sep 2005
Gate
t
F3