AT17F16-30BJI Atmel, AT17F16-30BJI Datasheet
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AT17F16-30BJI
Specifications of AT17F16-30BJI
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AT17F16-30BJI Summary of contents
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... Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. Table 1-1. AT17F Series Packages Package 8-lead LAP 20-lead PLCC 44-lead TQFP ® ® FLEX , APEX XC3000, XC4000, XC5200, Spartan AT17F16 Yes Yes Yes FPGA ™ Devices, ® ® , Virtex FPGAs, Configuration Flash Memory AT17F16 3392F–CNFG–2/08 ...
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... Pin Configuration AT17F16 2 8-lead LAP DATA 1 8 VCC CLK 2 7 SER_EN RESET/OE CEO (A2 GND 20-lead PLCC CLK RESET/ PAGESEL1 TQFP SER_EN PAGE_EN READY CEO (A2 READY 3392F–CNFG–2/08 ...
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... When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. 3392F–CNFG–2/08 Clock/Oscillator Reset Serial Download Logic 2-wire Serial Programming CE/WE/OE Data Control Logic Address AT17F16 CLK Logic CEO(A2) DATA CE RESET/OE SER_EN 3 ...
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... PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no effect. Notes: AT17F16 4 Pin Description I/O I – – 1. This pin has an internal 20 kΩ pull-up resistor. 2. This pin has an internal 30 kΩ pull-down resistor. AT17F16 8 20 LAP PLCC – 16 – 11 – – ...
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... Address Space 1. This pin has an internal 20 kΩ pull-up resistor. 2. This pin has an internal 30 kΩ pull-down resistor. AT17F16 Table 5-2. When AT17F16 (16 Mbits) 00000 – 3FFFFh 40000 – 7FFFFh 80000 – BFFFFh C0000 – FFFFFh 00000 – FFFFFh and GND is recommended. ...
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... The serial enable input must remain High during FPGA configuration operations. Bringing SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied +3.3V (±10%). Notes: AT17F16 This pin has an internal 20 kΩ pull-up resistor. 2. This pin has an internal 30 kΩ pull-down resistor. 3392F–CNFG–2/08 ...
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... RESET/OE on each configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level. 3392F–CNFG–2/08 or allowed to float to logic High via the internal pull- AT17F16 Table 5 ...
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... The AT17F Series Configurators enter a low-power standby mode whenever SER_EN is High and CE is asserted High. In this mode, the AT17F Configurator consumes less than cur- rent at 3.6V. The output remains in a high-impedance state regardless of the state of the OE input. AT17F16 8 supply only. Programming CC ...
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... Exposure to Abso- lute Maximum Rating conditions for extended periods of time may affect device reliability. AT17F Series Configurator Min Max 2.97 3.63 2.97 3.63 AT17F16 Min Max 2 0.8 2.4 0.4 2.4 ...
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... AC Characteristics CE RESET/OE CLK T CE DATA 15. AC Characteristics when Cascading RESET/OE CE CLK T DATA LAST BIT T CEO AT17F16 10 T SCE CAC CDF T OCK OCE T SCE T HCE T HOE FIRST BIT T OOE T OCE 3392F–CNFG–2/08 ...
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... Industrial Commercial 0 (1) Industrial 0 Commercial (1) Industrial Commercial 15 (1) Industrial 15 Commercial 15 (1) Industrial 15 Commercial 20 (1) Industrial 25 Commercial 0 (1) Industrial 0 Commercial 20 (1) Industrial 20 Commercial (1) Industrial Commercial (1) Industrial Commercial (1) Industrial Commercial (1) Industrial AT17F16 AT17F16 Typ Max Units MHz 10 MHz 33 MHz 33 MHz 12 µs 12 µ ...
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... Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial θ [° C/W] JC θ (1) [° C/W] JA θ [° C/W] JC θ (1) [° C/W] JA θ [° C/W] JC θ (1) [° C/W] JA AT17F16 Max Units MHz 33 MHz AT17F16 – – – – 3392F–CNFG–2/08 ...
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... Ordering Information Memory Size 16-Mbit Notes: 1. For the -30BJC and -30BJI packages, customers may migrate to the AT17F32-BJU. 2. For the -30JC and -30JI packages, customers may migrate to the AT17F16-30JU. 19. Green Package Options (Pb/Halide-free/RoHS Compliant) Memory Size 16-Mbit 8CN4 8-lead 1.04 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOIC Packages ...
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... Bottom View Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm Package Drawing Contact: packagedrawings@atmel.com AT17F16 14 D Pin1 Corner TITLE 8CN4, 8-lead ( 1.04 mm Body), Lead Pitch 1.27mm, Leadless Array Package (LAP) ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3392F–CNFG–2/08 PIN NO. 1 1.14(0.045) X 45˚ IDENTIFIER TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) AT17F16 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
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... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT17F16 TITLE 44A, 44-lead Body Size, 1 ...
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... E – August 2007 F – February 2008 3392F–CNFG–2/08 History Added last-time buy for AT17F16-30CC and AT17F16-30CI. Removed -30CC and -30CI devices from ordering information. Announced last-time buy for -30JC, -30BJC, -30JI, and -30BJI devices. Removed -30JC, -30JI, -30BJC and -30BJI devices from ordering information ...
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... AT17F16 18 3392F–CNFG–2/08 ...
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... AT17F16 19 ...
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