MD2533-D8G-X-P/Y SanDisk, MD2533-D8G-X-P/Y Datasheet - Page 75
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MD2533-D8G-X-P/Y
Manufacturer Part Number
MD2533-D8G-X-P/Y
Description
IC MDOC H3 8GB FBGA
Manufacturer
SanDisk
Type
Flash Disk Moduler
Specifications of MD2533-D8G-X-P/Y
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
8G (1G x 8)
Interface
Parallel
Voltage - Supply
1.65 V ~ 1.95 V, 2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
115-LFBGA
Density
1GByte
Operating Supply Voltage (typ)
1.8/3.3V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Package Type
FBGA
Mounting
Surface Mount
Pin Count
115
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
1.65/2.7V
Operating Supply Voltage (max)
1.95/3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Rev. 1.2
10.3.9 DMA Request Timing Diagram
10.3.9.1
Table 20 lists DMA request timing parameters and Figure 30 shows the DMA request timing
diagram in Asynchronous data transfer.
Notes: 1. Applies to EDGE mode only. The DMARQ# pulse width can be configured by SW.
10.3.9.2
Table 21 lists DMA request timing parameters and Figure 31 shows the DMA request timing
diagram in Synchronous data transfer.
Notes: 1. Applies to EDGE mode only. The DMARQ# pulse width can be configured by SW.
75
2. Applies to LEVEL mode only. Values refer to rising of CE or OE signal, which ever
2. Applies to LEVEL mode only.
DMARQ#
DM A R Q #
Tw(dmarq)
Tp(ce/oe)
Tw(dmarq)
Tp(bclk)
B C L K
CE/OE
negated first.
Timing is relative to the rising edge of CLK which samples CE# asserted.
CLK
Symbol
Symbol
Asynchronous Data Transfer
Synchronous Data Transfer
Table 20: DMA Request Timing Parameters (Asynchronous Data Transfer)
Table 21: DMA Request Timing Parameters (Synchronous Data Transfer)
Figure 30: DMA Request Timing Diagram (Asynchronous Data Transfer)
Figure 31: DMA request Timing Diagram (Synchronous Data Transfer)
DMARQ# pulse width
CE/OE to DMARQ#
negation
DMARQ# pulse width
CLK to DMARQ# negation
Description
Description
2
Tw(dmarq)
Tw(dmarq)
1
1
T w ( d m a r q )
T w ( d m a r q )
2
Tp(ce/oe)
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
Min
Min
20
19
20
17
1.8V
1.8V
Max
Max
Min
Min
20
16
20
13
T p ( b c lk)
3.3V
3.3V
Max
Max
Product Specifications
Units
Units
ns
ns
ns
ns
92-DS-1205-10