MD2533-D8G-X-P/Y SanDisk, MD2533-D8G-X-P/Y Datasheet - Page 44
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MD2533-D8G-X-P/Y
Manufacturer Part Number
MD2533-D8G-X-P/Y
Description
IC MDOC H3 8GB FBGA
Manufacturer
SanDisk
Type
Flash Disk Moduler
Specifications of MD2533-D8G-X-P/Y
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
8G (1G x 8)
Interface
Parallel
Voltage - Supply
1.65 V ~ 1.95 V, 2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
115-LFBGA
Density
1GByte
Operating Supply Voltage (typ)
1.8/3.3V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Package Type
FBGA
Mounting
Surface Mount
Pin Count
115
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
1.65/2.7V
Operating Supply Voltage (max)
1.95/3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Rev. 1.2
7.3.8 DPD Activation Register
Description:
Address (hex): 9416 (128KB window) / 1416 (8KB window)
Type:
7.3.9 DMA Control Register
Description:
Address (hex): 940E (128KB window) / 140E (8KB window)
Type:
44
WAKE_UP_SEL_BIT
Bit number
Read/Write
Bit name
Reset value
POWER_DN
Bit number
Read/Write R
Bit name
Reset value
PULSE_WIDTH
EDGE
DMA_POL
D15-D1
R
RFU
0
D15-D9
RFU
0
This 16-bit register is used to put mDOC H3 into Deep Power Down mode.
Read / Write
This 16-bit register controls the DMA_REQ signal to the host.
Read / Write
The width of the DMARQ# signal will be:
PULSE_WIDTH * ICMU_CLK (cycle). Maximum 32 ICMU clocks.
Note: If the value is zero then DMARQ# signal will not be asserted.
Level or Edge:
0: Level – DMARQ# will be asserted when data is ready and will be de-asserted
before the end of the data according to DMA_PROG_NEG (DMA Negation).
1: Edge – DMARQ# will be generated for the number of clock specified in the
PULSE_WIDTH field.
DMARQ# polarity:
0: active high
Setting this bit to ‘1’ will put the device to Deep Power Down mode.
D8-D4
R/W
PULSE_WIDTH RFU
4
Selects the device wake up trigger
0: mDOC H3 CE# is the wakeup trigger.
1: Read access (CE# & OE# assertion) or write access (CE# and WE#
assertion) is the wakeup trigger.
D3
R
0
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
D2
R/W
EDGE
0
D1
R/W
DMA_POL
1
D0
W
POWER_DN
0
mDOC H3 Registers
D0
R/W
DMA_EN
0
92-DS-1205-10