MD8331-D2G-V18-X-P/Y SanDisk, MD8331-D2G-V18-X-P/Y Datasheet - Page 48
![no-image](/images/manufacturer_photos/0/5/581/sandisk_sml.jpg)
MD8331-D2G-V18-X-P/Y
Manufacturer Part Number
MD8331-D2G-V18-X-P/Y
Description
IC MDOC G4 2GB 69-FBGA
Manufacturer
SanDisk
Datasheet
1.MD8832-D1G-V18-X-P.pdf
(85 pages)
Specifications of MD8331-D2G-V18-X-P/Y
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
2G (256M x 8)
Speed
33ns
Interface
Parallel
Voltage - Supply
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
69-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MD8831-D2G-V18-X-P/Y
MD8831-D2G-V18-X-P/Y
MD8832-D2G-V18-X-P/Y
MD8832-D2G-V18-X-P/Y
MD8831-D2G-V18-X-P/Y
MD8832-D2G-V18-X-P/Y
MD8832-D2G-V18-X-P/Y
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MD8331-D2G-V18-X-P/Y
Manufacturer:
SanDisk
Quantity:
10 000
7.18 MultiBurst Mode Control Register
Description:
Address (hex): 101C
48
Read/Write
Description
Reset Value
Read/Write
Description
Reset Value
Read/Write
Description
Reset Value
Bit No.
Bit No.
15-10
9-0
0
1
BST_EN (MultiBurst Mode Enable). Enables MultiBurst mode read cycles.
0: The CLK input is disabled and may be left floating. Burst read cycles are not supported.
1: The CLK input is enabled. Subsequent read cycles must be MultiBurst mode.
CLK_INV (Clock Invert). Selects the edge of the CLK input on which CE# and OE# are
sampled.
0: CE# and OE# are sampled on the rising edge of CLK.
1: CE# and OE# are sampled on the falling edge of CLK, and there will be an additional ½
NEGATE_COUNT. When the EDGE bit of the DMA Control register[0] is 0, this field must
Reserved for future use.
be programmed to specify the bus cycle in which DMARQ# will be negated, as follows:
NEGATE_COUNT = BYTES_REMAINING + 16 + BYTES_PER_CYCLE.
Example: To negate DMARQ# at the beginning of the cycle in which the last word is to be
transferred by a 16-bit host: NEGATE_COUNT = 2 + 16 + 2 = 20.
This 16-bit register controls the behavior of DiskOnChip G4 during MultiBurst
mode read cycles.
Bit 15
Bit 7
0
0
0
RFU_0
R
Bit 14
Bit 6
0
0
0
Bits 15-10
LENGTH
RFU_0
Data Sheet (Preliminary) Rev. 0.3
R
DMA Control Register [1]
LATPI
Bit 13
Bit 5
R
0
0
0
EBRA
Bit 4
Description
Description
12
R
0
0
0
R/W
Bit 11
Bit 3
FIFO
R
0
0
0
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
NEGATE_COUNT
HOLD
Bit 10
Bit 2
0
0
0
LATENCY
Bits 9-0
R/W
CLK_INV
Bit 1
Bit 9
R/W
0
0
0
92-DS-1105-00
BST_EN
Bit 0
Bit 8
0
0
0