MD8331-D2G-V18-X-P/Y SanDisk, MD8331-D2G-V18-X-P/Y Datasheet - Page 46
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MD8331-D2G-V18-X-P/Y
Manufacturer Part Number
MD8331-D2G-V18-X-P/Y
Description
IC MDOC G4 2GB 69-FBGA
Manufacturer
SanDisk
Datasheet
1.MD8832-D1G-V18-X-P.pdf
(85 pages)
Specifications of MD8331-D2G-V18-X-P/Y
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
2G (256M x 8)
Speed
33ns
Interface
Parallel
Voltage - Supply
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
69-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MD8831-D2G-V18-X-P/Y
MD8831-D2G-V18-X-P/Y
MD8832-D2G-V18-X-P/Y
MD8832-D2G-V18-X-P/Y
MD8831-D2G-V18-X-P/Y
MD8832-D2G-V18-X-P/Y
MD8832-D2G-V18-X-P/Y
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MD8331-D2G-V18-X-P/Y
Manufacturer:
SanDisk
Quantity:
10 000
7.16 DPD Control Register
Description:
Address (hex): 107C
46
Read/Write
Description
Reset Value
Bit No.
7-3
3-0
6-4
1
2
7
output signal will be asserted until the completion of the download process.
PU_DIS (Pull-Up Disable). Controls the pull-up resistors D[15:8] as follows:
1: Always disable the pull-ups
0: Enable the pull-ups when IF_CFG = 0
TURBO. Activates turbo operation.
0: DiskOnChip is used in normal operation, without improved access time. Output buffers
1. DiskOnChip is used in Turbo operation. Output buffers are enabled immediately after the
Reserved for future use.
MODE[0:3]. Controls the behavior of the DPD input:
0000: DPD input is not used to control DPD mode
0001: DPD mode exited on rising edge of DPD input
0010: DPD mode exited on falling edge of DPD input
0100: DPD mode is entered when DPD=1 and exited when DPD=0
1000: DPD mode is entered when DPD=0 and exited when DPD=1
Reserved for future use.
PD_OK (Power- Down OK). This read-only bit indicates that it is currently possible to put
DiskOnChip G4 in Deep Power-Down mode.
This register specifies the behavior of the DPD input signal.
are enabled only after a long enough delay to guarantee that there will be no more than a
single transition on each bit.
assertion of OE# and CE#, resulting in improved access time. Read cycles from the
Programmable Boot Block may result in additional noise and power dissipation due to
multiple transitions on the data bus.
PD_OK
Bit 7
0
Bit 6
0
Data Sheet (Preliminary) Rev. 0.3
R
RFU_0
Bit 5
0
Bit 4
Description
0
Bit 3
0
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
Bit 2
0
MODE[0:3]
R/W
Bit 1
0
92-DS-1105-00
Bit 0
0