CY7C1250V18-333BZXC Cypress Semiconductor Corp, CY7C1250V18-333BZXC Datasheet - Page 23

• Manufacturer Part Number: CY7C1250V18-333BZXC
• Description: IC SRAM 36MBIT 333MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1250V18-333BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 36M (1M x 36)
• Speed: 333MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Read/Write/Deselect Sequence
Notes
Document Number: 001-06348 Rev. *D
QVLD
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
29. Outputs are disabled (High-Z) one clock cycle after a NOP.
30. The third NOP cycle between read to write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency
R/W
DQ
CQ
CQ
LD
operation, it may be required to avoid bus contention.
A
K
K
NOP
1
t KH
(Read Latency = 2.0 Cycles)
t KL
t
t SA t HA
SC
A0
READ
2
t HC
t CYC
A1
t
QVLD
READ
3
t
t CQOH
KHKH
t
[28, 29, 30]
CLZ
t CQOH
Figure 5. Waveform for 2.0 Cycle Read Latency
4
NOP
t CO
Q00
t CCQO
Q01 Q10
t
t
CCQO
QVLD
5
NOP
t DOH
Q11
t
t CQD
CQDOH
NOP
6
t
CHZ
A2
WRITE
7
t SD
t HD
D20 D21
A3
WRITE
CY7C1246V18, CY7C1257V18
CY7C1248V18, CY7C1250V18
8
t CQH
t SD
D30
A4
9
READ
t
CQHCQH
D31
t
HD
DON’T CARE
t
QVLD
10
NOP
11
NOP
UNDEFINED
Q40 Q41
Page 23 of 27
12
[+] Feedback
[+] Feedback