M28W640HCB70N6F NUMONYX, M28W640HCB70N6F Datasheet
M28W640HCB70N6F
Specifications of M28W640HCB70N6F
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M28W640HCB70N6F Summary of contents
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... Electronic signature – Manufacturer code: 20h – Top device code, M28W640HCT: 8848h – Bottom device code, M28W640HCB: 8849h November 2008 M28W640HCT M28W640HCB 64 Mbit ( 16, boot block supply Flash memory FBGA TFBGA48 (ZB) 6.39 x 10.5 mm TSOP48 ( Packages – RoHS compliant Rev 3 1/72 www.numonyx.com 1 ...
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... Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 Double Word Program command ...
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Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.11 Program/Erase Resume command . . ...
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Appendix C Flowcharts and pseudocodes Appendix D Command interface and ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. TFBGA connections (top view through package Figure 4. Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Protection register memory map Figure 6. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 7. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 9. Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 10. ...
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... The device includes a 192-bit protection register to increase the protection of a system design. The protection register is divided into a 64-bit segment and a 128-bit segment. The 64-bit segment contains a unique device number written by Numonyx, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected ...
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Figure 1. Logic diagram Table 1. Signal names Name A0-A21 DQ0-DQ15 8/ A0-A21 W E M28W640HCT M28W640HCB Description ...
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Figure 2. TSOP connections A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 A19 A18 A17 All V pins must be connected to the power supply. ...
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Figure 3. TFBGA connections (top view through package A13 B A14 C A15 D A16 All V pins must be connected to the power supply All V pins must ...
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... Kwords 3F0000 00FFFF 32 Kwords 008000 007FFF 32 Kwords 000000 1. Also see Appendix A, Tables 23 and Figure 5. Protection register memory map PROTECTION REGISTER 8Ch User programmable OTP 85h 84h Unique device number 81h Protection register lock 80h M28W640HCB Bottom boot block addresses 3FFFFF 32 Kwords ...
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... Figure 1: Logic diagram connected to this device. 2.1 Address inputs (A0-A21) The Address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the internal state machine. 2.2 ...
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... Chip Enable or a change of the address is required to ensure valid data outputs. 2.8 V supply voltage DD V provides the power supply to the internal core and the I/O pins of the memory device the main power supply for all operations (read, program and erase). 2.9 V program supply voltage ...
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... Read Read bus operations are used to output the contents of the memory array, the Electronic Signature, the Status Register and the common Flash interface. Both Chip Enable and Output Enable must should be used to enable the device. Output Enable should be used to gate data onto the output ...
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... Reset During Reset mode when Output Enable is Low, V outputs are high impedance. The memory is in Reset mode when Reset consumption is reduced to the standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to V operation is aborted and the memory content is no longer valid. ...
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... Read Memory Array command The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode ...
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... Read CFI Query command The Read Query command is used to read data from the common Flash interface (CFI) memory area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query command. Once the command is issued subsequent bus read operations read from the common Flash interface memory area ...
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... The third bus cycle latches the address and the data of the second word to be written and starts the Program/Erase controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to V program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix ...
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... The fifth bus cycle latches the address and the data of the fourth word to be written and starts the Program/Erase controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to V program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix ...
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... Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 5: Protection register memory Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. ...
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Block Unlock command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command: The first bus cycle sets up ...
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... Table 4. Commands Commands 1st cycle Op. Add Data Read Memory 1+ Write X Array Read Status 1+ Write X Register Read Electronic 1+ Write X Signature Read CFI 1+ Write X Query Erase 2 Write X 40h or Program 2 Write X Double Word 3 Write X (3) Program Quadruple Word 5 Write X (4) Program Clear Status 1 Write ...
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Table 5. Read electronic signature Code Device Manufacturer V code M28W640HCT V Device code M28W640HCB Table 6. Read block lock signature Block status Locked block ...
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Table 8. Program, Erase times and Program/Erase endurance cycles Parameter Word Program Double Word Program Quadruple Word Program Main Block Program Parameter Block Program Main Block Erase Parameter Block Erase Program/Erase cycles (per block) 1. Typical time to program a ...
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Block locking The M28W640HCT and M28W640HCB feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection: Lock/unlock - this first level allows ...
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Lock-down state Blocks that are Locked-down (state (0,1,x)) are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-down by ...
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Table 10. Protection status (1) Current Protection status (WP, DQ1, DQ0) Program/Erase Current state allowed 1,0,0 yes (2) 1,0,1 no 1,1,0 yes 1,1,1 no 0,0,0 yes (2) 0,0,1 no 0,1 The lock status is defined by the write ...
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... The Erase Suspend status bit indicates that an erase operation has been suspended or is going to be suspended. When the Erase Suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase controller status bit is High (Program/Erase controller inactive). Bit 7 is set within 30 μ ...
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... Erase status (bit 5) The Erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase status bit is High (set to ‘1’), the Program/Erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly ...
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Block Protection status (bit 1) The Block Protection status bit can be used to identify if a program or erase operation has tried to modify the contents of a locked block. When the Block Protection status bit is High ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 12. ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the ...
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Table 14. Capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Test condition Min OUT Max Unit 33/72 ...
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Table 15. DC characteristics Symbol Parameter I Input Leakage current LI I Output Leakage current LO I Supply current (Read) DD Supply current (Standby or Automatic I DD1 Standby) I Supply current (Reset) DD2 I Supply current (Program) DD3 I ...
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Figure 8. Read AC waveforms A0-A21 tAVQV E tELQV tELQX G tGLQX DQ0- DQ15 ADDR. VALID CHIP ENABLE Table 16. Read AC characteristics Symbol Alt t t Address valid to Next Address Valid AVAV Address valid to ...
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Figure 9. Page Read AC waveforms 36/72 ...
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Figure 10. Write AC waveforms, Write Enable controlled 37/72 ...
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Table 17. Write AC characteristics, Write Enable controlled Symbol Alt t t AVAV AVWH DVWH ELWL CS t ELQV (1)(2) t QVVPL t QVWPL ( VPHWH VPS t t ...
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Figure 11. Write AC waveforms, Chip Enable controlled 39/72 ...
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Table 18. Write AC characteristics, Chip Enable controlled Symbol Alt t t AVAV AVEH DVEH EHAX EHDX EHEL CPH t EHGL t t EHWH WH ...
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Figure 12. Power-up and Reset AC waveforms tPHWL tPHEL tPHGL RP tVDHPH V DD Power-up Table 19. Power-up and Reset AC characteristics Symbol Parameter t PHWL Reset High to Write Enable Low, t PHEL Chip Enable Low, ...
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... Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages. RoHS compliant packages are lead-free. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Figure 14. TFBGA48 6. ball array, 0.75 mm pitch, bottom view package outline BALL "A1" Drawing is not to scale. Table 21. TFBGA48 6.39 x 10.5 mm ...
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... F = RoHS compliant package, tape & reel packing Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 44/72 M28W640HCT 70 N ...
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Appendix A Block address tables Table 23. Top boot block addresses, M28W640HCT # ...
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Table 23. Top boot block addresses, M28W640HCT (continued ...
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Table 23. Top boot block addresses, M28W640HCT (continued) # Size (Kword ...
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Table 23. Top boot block addresses, M28W640HCT (continued) # 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 ...
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Table 24. Bottom boot block addresses, M28W640HCB # Size (Kword) 134 32 133 32 132 32 131 32 130 32 129 32 128 32 127 32 126 32 125 32 124 32 123 32 122 32 121 32 120 32 ...
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Table 24. Bottom boot block addresses, M28W640HCB (continued ...
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Table 24. Bottom boot block addresses, M28W640HCB (continued) # Size (Kword ...
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Table 24. Bottom boot block addresses, M28W640HCB (continued 52/72 ...
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... The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 30: Security code by the final user impossible to change the security number after it has been written by Numonyx. Issue a Read command to return to Read mode. Table 25. Query structure overview Offset ...
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... Address for primary algorithm extended query table (see Alternate vendor command set and control interface ID code second vendor - specified algorithm supported (0000h means none exists) Address for Alternate algorithm extended query table (0000h means none exists) Value Numonyx Top Bottom ‘Q’ ‘R’ ‘Y’ Intel ...
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Table 27. CFI query system interface information Offset Data V logic supply minimum program/erase or write voltage DD 1Bh 0027h bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV V logic supply maximum Program/Erase ...
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Table 28. Device geometry definition Offset Word Data Mode 27h 0017h 28h 0001h 29h 0000h 2Ah 0003h 2Bh 0000h 2Ch 0002h 2Dh 007Eh 2Eh 0000h 2Fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h 0020h 34h 0000h 2Dh 0007h 2Eh ...
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Table 29. Primary algorithm-specific extended query table Offset Data ( 35h (P+0)h = 35h 0050h (P+1)h = 36h 0052h Primary algorithm extended query table unique ASCII string ‘PRI’ (P+2)h = 37h 0049h (P+3)h = 38h 0031h Major version ...
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Table 29. Primary algorithm-specific extended query table (continued) Offset Data ( 35h (P+F)h = 44h 0080h Protection field 1: protection description (P+10)h = 45h 0000h (P+11)h = 46h 0003h (P+12)h = 47h 0004h (P+13)h = 48h 1. See ...
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... If an error is found, the Status Register must be cleared before further Program/Erase controller operations. program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10 writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 ...
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... Address 1 and address 2 must be consecutive addresses differing only for bit A0. 60/72 double_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; /*Memory enters read status state after the Program command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1, 2) error_handler ( ) ...
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... Address 1 to address 4 must be consecutive addresses differing only for bits A0 and A1. quadruple_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (any_address, 0x56) ; writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; writeToFlash (addressToProgram3, dataToProgram3) ; writeToFlash (addressToProgram4, dataToProgram4) ; /*Memory enters read status state after the Program command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ; ...
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Figure 18. Program Suspend & Resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another address Write D0h Program Continues 62/72 program_suspend_command ...
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... YES End error is found, the Status Register must be cleared before further program/erase operations. erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0 only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 Invalid if (status_register ...
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Figure 20. Erase Suspend & Resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock ...
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Figure 21. Locking operations flowchart and pseudocode Start Write 60h Write 01h, D0h or 2Fh Write 90h Read Block Lock States NO Locking change confirmed? YES Write FFh End locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; /*configuration setup*/ if ...
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... Status check of b1 (protected block after a sequence error is found, the Status Register must be cleared before further Program/Erase controller operations. 66/72 protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ; writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 Invalid if (status_register ...
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Appendix D Command interface and Program/Erase controller state . Table 31. Write state machine current/next SR Current Data when Read bit state Read 7 Array (FFh) Read Read Array ‘1’ Array Array Read Read ‘1’ Status Status Array Read Electronic ...
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Table 31. Write state machine current/next SR Current Data when Read bit state Read 7 Array (FFh) Prog. Prog. Sus Sus ‘1’ CFI Read CFI Read Array Program Read ‘1’ Status (complete) Array Erase ‘1’ Status Setup Erase Read ‘1’ ...
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Table 32. Write state machine current/next Current Read Read CFI state Elect.Sg. Query (90h) (98h) Read Read CFI Read Array Elect.Sg. Query Read Read CFI Read Status Elect.Sg. Query Read Read Read CFI Elect.Sg. Elect.Sg. Query Read CFI Read ...
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Table 32. Write state machine current/next Current Read Read CFI state Elect.Sg. Query (90h) (98h) Erase Setup Erase Read Read CFI Cmd.Error Elect.Sg. Query Erase (continue) Erase Erase Erase Suspend Suspend Suspend Read Read CFI Read Ststus Elect.Sg. Query Erase ...
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... Revision history Table 33. Document revision history Date Version 29-Jan-2008 20-Mar-2008 06-Nov-2008 1 Initial release. 2 Applied Numonyx branding. Changed title page to remove “preliminary” status. 3 Corrected minimum voltage for V Changes in Table 15.: DC characteristics IH 71/72 ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...