CY7C1565V18-400BZC Cypress Semiconductor Corp, CY7C1565V18-400BZC Datasheet - Page 6

• Manufacturer Part Number: CY7C1565V18-400BZC
• Description: IC SRAM 72MBIT 400MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1565V18-400BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (2M x 36)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Document Number: 001-05384 Rev. *F
D
WPS
NWS
NWS
BWS
BWS
BWS
BWS
A
Q
RPS
QVLD
K
K
CQ
CQ
Pin Name
[x:0]
[x:0]
0
1
2
3
0
1
,
,
,
,
,
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Valid output
Echo Clock
Echo Clock
Outputs-
indicator
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
Clock
IO
Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
CY7C1561V18 − D
CY7C1576V18 − D
CY7C1563V18 − D
CY7C1565V18 − D
Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the Write Port. Deselecting the write port ignores D
Nibble Write Select 0, 1− Active LOW (CY7C1561V18 Only). Sampled on the rising edge of the K and
K clocks when write operations are active. Used to select which nibble is written into the device during
the current portion of the write operations. NWS
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks when
write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1576V18 − BWS
CY7C1563V18 − BWS
CY7C1565V18 − BWS
BWS
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
8M x 8 (4 arrays each of 2M x 8) for CY7C1561V18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1576V18,
4M x 18 (4 arrays each of 1M x 18) for CY7C1563V18 and 2M x 36 (4 arrays each of 512K x 36) for
CY7C1565V18. Therefore, only 21 address inputs are needed to access the entire memory array of
CY7C1561V18 and CY7C1576V18, 20 address inputs for CY7C1563V18, and 19 address inputs for
CY7C1565V18. These inputs are ignored when the appropriate port is deselected.
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of both the K and K clocks during read operations. On deselecting the read
port, Q
CY7C1561V18 − Q
CY7C1576V18 − Q
CY7C1563V18 − Q
CY7C1565V18 − Q
Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the K clock. Each read access consists of a burst of four sequential transfers.
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR-II+. The timings for the echo clocks are shown in the
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR-II+. The timings for the echo clocks are shown in the
2
controls D
[x:0]
are automatically tri-stated.
[26:18]
[7:0]
[8:0]
[17:0]
[35:0]
[7:0]
[8:0]
[17:0]
[35:0]
0
0
0
and BWS
controls D
controls D
controls D
[x:0]
.
[x:0]
3
controls D
[8:0]
[8:0]
[8:0]
. All accesses are initiated on the rising edge of K.
, BWS
and BWS
Pin Description
1
[35:27].
controls D
0
1
controls D
controls D
CY7C1561V18, CY7C1576V18
CY7C1563V18, CY7C1565V18
[17:9]
[3:0]
[17:9].
,
and NWS
Switching Characteristics
Switching Characteristics
1
controls D
[7:4]
.
Page 6 of 28
on page 23.
on page 23.
[x:0]
.
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