CY7C1565V18-400BZC Cypress Semiconductor Corp, CY7C1565V18-400BZC Datasheet - Page 28

• Manufacturer Part Number: CY7C1565V18-400BZC
• Description: IC SRAM 72MBIT 400MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1565V18-400BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (2M x 36)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document History Page
© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-05384 Rev. *F
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document Title: CY7C1561V18/CY7C1576V18/CY7C1563V18/CY7C1565V18, 72-Mbit QDR™-II+ SRAM 4-Word Burst Archi-
tecture (2.5 Cycle Read Latency)
Document Number: 001-05384
REV.
*A
*B
*C
*D
*E
*F
**
ECN NO.
1351243 See ECN
2181046 See ECN VKN/AESA Added footnote# 22 related to I
402911
425251
437000
461934
497567
See ECN
See ECN
See ECN
See ECN
See ECN
ISSUE
DATE
ORIG. OF
CHANGE
VKN/FSU
NXR
NXR
VEE
VEE
IGS
DESCRIPTION OF CHANGE
New Data Sheet
Updated the switching waveform
Corrected the typos in DC parameters
Updated the DLL section
Added additional notes in the AC parameter section
Updated the Power up sequence
Added additional parameters in the AC timing
ECN for Show on web
Moved the Selection Guide table from page# 3 to page# 1.
Modified Application Diagram.
Changed t
from 10 ns to 5 ns and changed t
Characteristics table
Modified Power Up waveform.
Included Maximum ratings for Supply Voltage on V
Changed the Maximum Ratings for DC Input Voltage from V
Changed the Pin Definition of I
page#18.
Changed the V
Operating Range table and in the DC Electrical Characteristics table
Added foot note in page# 1
Changed the Maximum rating of Ambient Temperature with Power Applied from –10°C
to +85°C to –55°C to +125°C
Changed V
table and in the note below the table
Updated footnote #21 to specify Overshoot and Undershoot Spec
Updated I
Updated Θ
Removed x9 part and its related information
Updated footnote #25
Converted from preliminary to final
Added x8 and x9 parts
Changed t
Updated footnote# 23
Updated Ordering Information table
DD
TH
CYC
JA
REF
and I
and t
and Θ
max spec to 8.4 ns for all speed bins
DDQ
Revised March 6, 2008
(Max) spec from 0.85V to 0.95V in the DC Electrical Characteristics
SB
TL
JC
operating voltage to 1.4V to V
from 40 ns to 20 ns, changed t
values
values
X
DD
from Input Load current to Input Leakage current on
TDOV
CY7C1561V18, CY7C1576V18
CY7C1563V18, CY7C1565V18
from 20 ns to 10 ns in TAP AC Switching
DD
DDQ
TMSS
in the Features section, in
Relative to GND.
, t
TDIS
DDQ
, t
CS
to V
, t
DD
TMSH
.
Page 28 of 28
, t
TDIH
, t
CH
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